JPH0417193A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To make an output of a sense amplifier stable by controlling a level of 1st and 2nd output signals outputted from a sense amplifier at data write by a write amplifier to be a prescribed different level respectively. CONSTITUTION:While a sense amplifier 8 is disconnected from bit lines B1, B2, a level of the bit line B1 is clamped to a low level, a level difference is produced between the bit lines B1 and B2 by a resistor R3 provided between the sense amplifier 8 and a line interruption switch 10 and a level difference is caused between levels of data buses DB, inverse of DB outputted from the sense amplifier 8 to the output buffer 7 and an output from the sense amplifier 8 does not reach an intermediate level but a prescribed output level is obtained. Thus, the level of the output signal from the sense amplifier 8 is stably outputted.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor memory device that stabilizes the output of a sense amplifier during data writing and thereby speeds up the operation of a memory cell array. A predetermined memory cell selected from among them and connected to a pair of first and second bit lines, and a predetermined memory cell connected to the first and second bit lines, based on the potential difference between these two bit lines. a sense amplifier that outputs data written to the memory cell as first and second output signals at a predetermined potential level; and a sense amplifier connected to the first and second bit lines to write data to the predetermined memory cell. When the write amplifier writes data to the memory cell, the sense amplifier is used as the first
and a means for electrically disconnecting from the second bit line, the potential levels of the first and second output signals outputted from the sense amplifier when writing data by the write amplifier are set to each other. A configuration is provided in which control means is provided for controlling to different predetermined potential levels.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more specifically, for example,
The present invention relates to a semiconductor memory device that is suitable for use in the field of Bi-CMO3 RAM and that reads data in memory at high speed.

In recent years, Bi-CMO has been developed which combines the low power consumption of CMOS devices with the high load driving ability of bipolar devices.
A large number of semiconductor memory devices of type 3 have been developed.

Such semiconductor memory devices are required to be faster as, for example, the processing speed of computers increases.

[Conventional technology]

As a conventional semiconductor memory device of this type, for example,
．． 5, in which 1 is a row address buffer, 2 is a row decoder, 3 is a memory cell array, 4 is a column address buffer, 5 is a column decoder, 6 is an amplifier section, and 7 is an output section. It's a hippo sofa. The memory cell array 3 is composed of a plurality of word lines, a hit line, and a plurality of memory cells (not shown) connected to these and arranged in a matrix. When writing or reading is performed by selecting one of multiple memory cells, the row decoder 2 selects one of the multiple word lines based on data input from the input terminal via the row address buffer 1. Based on the data input via the column address buffer 4, the column decoder 5 selects one of the plurality of bit lines, thereby selecting a specific one of the plurality of memory cells. Next, information is written to or read from the selected memory cell. The read information is taken out to the outside via the amplifier section 6 and the output buffer 7.

The specific circuit configuration of the main part of FIG. 4 will be explained based on FIG.
Bipolar I transistors 1. Q2, N channel MO3
) Bipolar transistor Ql via transistor Ns
, a sense amplifier 8 consisting of a current source 11 and a bipolar transistor Ql connected to the emitters of Q2, and resistors R1 and R2 connected to the bases of Q2, and a write amplifier consisting of an inverter W2 connected to the bit line pair, respectively. It consists of 9. Furthermore, memory cell array 3
has a plurality of memory cells CEL connected to bit lines B1 and B2 as data lines.

To explain the write operation in this semiconductor memory device, first, a word driver (not shown) is activated by the row decoder 2 based on address information sent from the row address buffer 1, and a word driver (not shown) is activated to write to a specific word line (not shown). ) is selected, and the column address buffer 4 and column decoder 5 select specific bit lines B1 and B2, thereby selecting a specific memory cell. Next, the state of the selected memory cell CEL is forcibly rewritten by the write amplifier 9.

To explain the rewriting operation in detail, in the conventional example shown in FIG.
It consists of an upped logic) circuit, and the positive voltage is connected to the ground level (hereinafter referred to as GND).
And a negative power supply is added as a negative voltage. Then, by using the write amplifier 9, for example, by lowering the bit line B2 connected to the memory cell CEL to GND and lowering the bit line B1 to the negative power supply, the memory cell CEL
is inverted, and the state of the memory cell CEL is forcibly rewritten.

However, in the conventional example shown in FIG. 5, the potentials of the bit lines Bl and B2 in the read state are close to GND, and the emitter of the bipolar transistor L1 and B2 is connected to the higher one of B1 and B2. The potential is 781 times lower than that of the transistor. That is, as described above, when the state changes from the read state to the write state, a negative power supply is directly applied to the base of the bipolar transistor 01, and the base-emitter of the bipolar transistor Q1 becomes reverse biased.

Therefore, there were reliability problems such as the old bipolar transistor becoming easily broken and having a shortened lifespan. In order to solve this problem, a semiconductor memory device as shown in FIG. 6 has been provided.

In the conventional example shown in FIG. 6, N-channel MO3) transistors Nl, N
A line cutoff switch 10 consisting of two memory cells (
, when writing to EL, the line cutoff switch 10 disconnects the bit lines Bl, B2 and the sense amplifier 8.
This is to prevent the problem of a negative power supply being directly applied to the base of the bipolar transistor Q1.

Note that C is a control terminal for applying a control signal to the line cutoff switch 10.

[Problem to be solved by the invention]

However, in such a conventional semiconductor memory device, when performing a write operation to the memory cell CEL, the sense amplifier 8 is connected to the bit line Bl.

Since the configuration was such that the sense amplifier 8 is completely disconnected from the bit lines B1 and B2, the base potentials of the bipolar transistors Ql and Q2 of the sense amplifier 8 are at the same potential when the sense amplifier 8 is disconnected from the bit lines Bl and B2, that is, the sense amplifier 8 The potentials of the data buses DB and DB outputted from the output buffer 7 to the output buffer 7 are also at the same potential, and the output buffer 7 is output at an intermediate level between "IP and L". In this way, if the output from the sense amplifier 8 becomes an intermediate level output when performing a write operation, a glitch will occur during the read operation in the next cycle, that is, when the state changes from the write state to the read state. This can easily lead to unstable operation. Therefore, for example,
As shown in FIG. 7, when the logic level is inverted by mistake, there is a delay time T until the logic level becomes the correct one.
This causes a problem in that the memory access time until data is read is delayed by this delay time T9, making it impossible to perform a high-speed read operation.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor memory device that stabilizes the output of a sense amplifier by controlling the potential level of the output signal of the sense amplifier to a predetermined potential level during a data write operation. There is.

[Means to solve the problem]

In order to achieve the above object, a semiconductor memory device according to the present invention includes a predetermined memory cell selected from a memory cell array and connected to a pair of first and second bit lines;
and a sense amplifier connected to the second bit line and outputting the data written in the memory cell as first and second output signals at a predetermined potential level based on the potential difference between these two focus lines; A write amplifier is connected to the first and second bit lines and writes data to the predetermined memory cell, and when the write amplifier writes data to the memory cell, the sense amplifier is connected to the first and second bit lines. and means for electrically disconnecting from the line, the potential levels of the first and second output signals output from the sense amplifier when writing data by the write amplifier are set to different predetermined potential levels. The configuration is such that a control means is provided for controlling.

[Effect]

In the present invention, even when the sense amplifier is electrically disconnected from the data line when data is written to the memory cell by the write amplifier, the potential level of the output signal from the sense amplifier is set to a different predetermined potential level by the control means. controlled.

Therefore, the potential level of the output signal from the sense amplifier is stable.

Furthermore, the conventional delay time is eliminated, and the operation speed is increased.

[Example] Hereinafter, the present invention will be explained based on the drawings.

FIG. 1 is a circuit diagram showing a main part configuration of a first embodiment of a semiconductor memory device according to the present invention. In FIG. 1, the same numbers as in the conventional example shown in FIG. 6 indicate the same or corresponding parts. Note that the overall configuration of the present invention is the same as the block diagram showing the overall configuration of a conventional semiconductor memory device shown in FIG.

First, the specific circuit configuration of the first embodiment will be explained based on FIG. 1.

In FIG. 1, this device is roughly divided into a memory cell array 3, an amplifier section 6, and an output buffer 7, and includes the amplifier section 6, a sense amplifier 8, a write amplifier 9, a line cutoff switch 1o, and a resistor as a control means. It consists of R3. Note that the resistor R3 has a value sufficiently larger than the resistors RI and R2 that does not affect the reading operation, and is connected to the bit line B1 between the sense amplifier 8 and the line cutoff switch 10. In this example,
Compared to the conventional example shown in FIG. 6, this embodiment is characterized in that a resistor R3 serving as a control means is connected to the bit line B1 between the sense amplifier 8 and the line cutoff switch 10.

Therefore, when the sense amplifier 8 is disconnected from the bit lines Bl and 82, the potential on the bit line B1 side is clamped to a low level, so that the resistor R3 provided between the sense amplifier 8 and the line cutoff switch 10 A potential difference is generated between each bit line Bl and 82, and the sense amplifier 8
Each data bus DB, D output from to the output buffer 7
A potential difference also occurs in the potential of B, and the output from the sense amplifier 8 does not become an intermediate level, but a predetermined output potential is obtained.

In other words, during a read operation in a cycle after a write operation, that is, when the state changes from a write state to a read state, it is possible to prevent memory access time from increasing due to delay time, and data can be read at high speed. .

FIG. 2 is a diagram showing a second embodiment of the semiconductor memory device according to the present invention. In FIG. 2, the same numbers as in the first embodiment shown in FIG. 1 indicate the same or corresponding parts.

A specific circuit configuration of the second embodiment will be explained based on FIG. 2.

In this embodiment, an N channel MOS which is an active element is used instead of the resistor R3 which is a passive element in the first embodiment shown in FIG.
A transistor Nc is connected to the bit line B2 between the sense amplifier 8 and the line cutoff switch 10, and a dummy Nc is connected to the bit line B1 between the sense amplifier 8 and the line cutoff switch 10, and is always in an off state. channel MO3)
The feature lies in the part where the transistor Nd is connected. Note that the N-channel MO3) transistor Nd is the same as the N-channel MO3) transistor Nc, so that the load capacitances attached to each bit line B1 and B2 are balanced equally.

Therefore, the N-channel MO provided on bit line B2
Similar to the first embodiment, the 3I-transistor Nc causes a potential difference between the bit lines Bl and 82 even when the sense amplifier 8 is disconnected from the bit lines Bl and B2, so that the output from the sense amplifier 8 becomes intermediate. level, and a predetermined output potential is obtained.

In addition, a dummy N-channel MO installed in the old human line
3I - Each bit line Bl by a transistor Nd.

By equalizing the balance of the load capacitances attached to B2, the access speed is improved, and faster operation can be expected compared to the first embodiment.

FIG. 3 is a diagram showing a third embodiment of the semiconductor memory device according to the present invention. In FIG. 3, the same numbers as in the first embodiment shown in FIG. 1 indicate the same or corresponding parts.

First, the configuration will be explained.

FIG. 3 is a circuit diagram showing a specific circuit configuration of the third embodiment. In FIG. 3, as in FIG. , a bipolar transistor Oc as a control means, and outputs from a plurality of sense amplifier circuits similar to the one shown in FIG. 1 provided for each bit line pair are connected to a data bus DB.

It is commonly connected to the DB. The memory cell array 3 includes a plurality of memory cells CELI, . ..., +
Q1n+port 2n, bipolar transistors Qsl, Q2n, . . . +Qsn, which receive the output of the column decoder;
The light amplifier 9 is an inverter WILW21. ---. W
in, W2n, line cutoff switch 10 is N channel M
O3) Transistors N11, N21. ...+Nln,
It consists of N2n. Bipolar transistor Qc
The collector is connected to the data bus DB, the emitter is connected to the current source 11, and the emitters of the bipolar transistors Qsl+...Qsn are commonly connected. In addition, Bll, B21. ...Bln and B2n are bit lines.

In this embodiment, the bipolar transistors sl, Qs2 . ... Qsn and a bipolar transistor Oc as a control means are combined into one ECL (emitt
It can be viewed as a circuit (coupled logic), in which current flows only through the bipolar transistor to which the highest potential is applied to the base.

That is, during the read operation, the bipolar transistor Q
"L" is applied to the base of c, and the sense amplifier to which the highest potential is applied among the pievora transistors Q s 1 + Q s 2 + . . . , Qsn is activated, and the pig is read out. During a write operation, 11 H++ is applied to the base of the bipolar transistor Qc, which turns on the bipolar transistor Oc and causes G
A current flows through the path of ND line→resistor R2→bipolar transistor Qc→current source 11. Therefore, the collector potential of this bipolar transistor Qc is fixed at a low level, while the data bus DB through which no current flows is fixed at a high level.

Therefore, in this embodiment, there is no need to provide a control means for each bit line pair as in the above-mentioned Embodiment 1.2, and it is only necessary to provide one control means for a plurality of bit line pairs. 1. The circuit configuration can be simplified compared to the second embodiment.

As described above, in this embodiment, the potential level of the output signal from the sense amplifier can be output stably, so even when the state changes from the write state to the read state, the operation of the sense amplifier becomes unstable. It is possible to prevent a decrease in memory access speed due to delay time caused by the state, and as a result, data in the memory can be read out at high speed without sacrificing high-speed performance of the semiconductor memory device.

In addition, in the above embodiment, the positive voltage is set to GND, and the ECL (emit
Although the explanation is given using a semiconductor storage device configured with a (ter coupled logic) circuit as an example, the circuit is not limited to this; Needless to say, it is freely determined depending on the configuration.

〔Effect of the invention〕

According to the present invention, the potential level of the output signal from the sense amplifier can be output stably, and data in the memory can be read out at high speed even when the state changes from the write state to the read state.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a main part configuration of a first embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing a main part structure of a second embodiment of a semiconductor memory device according to the present invention, FIG. 3 is a circuit diagram showing the main structure of a third embodiment of a semiconductor memory device according to the present invention, FIG. 4 is a block diagram showing the overall structure of a conventional semiconductor memory device, and FIG. 5 is a block diagram showing the overall structure of a conventional semiconductor memory device. FIG. 6 is a circuit diagram showing the main part configuration of a semiconductor memory device, FIG. 6 is a circuit diagram showing the main part structure of another conventional semiconductor memory device, and FIG. 7 is a circuit diagram showing the output state of the conventional sense amplifier. FIG. 3... Memory cell array, 6... Amplifier section, 7... Output sofa, 8... Sense amplifier, 9... Light amplifier, 10...Line cutoff switch, R3...Resistor (control means), Nc...N channel MO3) transistor (control means), Port C...Bipolar Transistor (control means)
, CEL, CELL, . . . , CELn - memory cell, Bl, B2. Bll...,...Bit line.

Claims (3)

[Claims] (1) A pair of first cells selected from the memory cell array.
and a predetermined memory cell connected to a second bit line, and a predetermined memory cell connected to the first and second bit lines, and based on the potential difference between these two bit lines, data written in the memory cell is written. a sense amplifier that outputs first and second output signals at a predetermined potential level; a write amplifier that is connected to the first and second bit lines and writes data into the predetermined memory cell; and the write amplifier. means for electrically disconnecting the sense amplifier from the first and second bit lines when data is written to the memory cell by the write amplifier; 1. A semiconductor memory device comprising a control means for controlling the potential levels of the first and second output signals to different predetermined potential levels. (2) The control means is a resistance element or a switching element connected to the first bit line, and when writing data, sets the potential of the first bit line to a potential different from the potential of the second bit. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is clamped at . (3) The control means is a control transistor having a collector connected to one of the first and second output signals and an emitter connected to an emitter of a transistor that controls on/off of the sense amplifier. The control transistor is forcibly turned on during data writing, thereby making the potential of one of the first and second output signals lower than the potential of the other of the first and second output signals. 2. The semiconductor memory device according to claim 1.