JPH04172012A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the noise of a power source by sensing that an output level is turned into an intermediate potential, and operating a current supply from the intermediate potential by an output transistor whose driving ability is high. CONSTITUTION:The input of a first inverter 1 is connected with an input terminal, the output is connected with the input of a first prebuffer 2, and the output of the first prebuffer 2 is connected with the input of a first output buffer 15. And also, the output of the first inverter 1 is inputted to the gates of first and second selected-circuits 21 and 22, and the output of the first selected-circuit 21 is connected with the input of a second inverter 16, and the output of the second selected-circuit 22 is connected with a third inverter 17. Moreover, the output of a second output buffer 23 which is constituted by connecting the output of the second inverter 16 with the input of a cascade-connected P channel transistor 13, and connecting the output of the third inverter 17 with the input of an N channel transistor 14, is connected with an output terminal. Thus, an output circuit in which a power inducing noise is reduced can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and more particularly to an output circuit that prevents a sudden current from flowing through an output transistor.

[Conventional technology]

As shown in FIG. 4, a conventional output circuit of this type has inverters 1 and 2 with different input threshold potentials corresponding to cascade-connected P-channel and N-channel transistors 3 and 4, respectively. , the transistors 3 and 4 are driven separately. As shown in FIG. 5, inverter 2. Assume that the threshold voltage is higher by ΔV7. As shown in the timing diagram of FIG. 5, when the input signal Vi to inverter 1 and inverter 2 rises, the output of inverter 2 is first output to N-channel output transistor 4, so N-channel output transistor 4 is turned off. become a state. After that, the input signal Vi
When V1 reaches the input threshold voltage Vil of the inverter 1 and the pressure of the inverter 1 is output to the P-channel output transistor 3, the P-channel output transistor 3 is turned on.

As described above, P channel output transistor 3 and N
Since channel output transistor 4 can be prevented from being turned on at the same time, no through current flows.

According to the same operating principle, when the input signal Vi is falling,
Since the N-channel output transistor 4 turns on after the P-channel output transistor 3 turns off, no large through current flows.

[Problem to be solved by the invention]

In the conventional output circuit described above, the through current is reduced, but the transistor connected to the output operates an external device, so the power supply capacity is large. Therefore, the pressure potential of the N-channel transistor 4 is ■ゎ. Since the P-channel transistor turns on when the output potential is at ground level, the current change d i / d t applied to the inductance of the power supply becomes large, and the noise induced in the power supply is large. There is. By the way,
According to the simulation results, 300a+V to GND
It was found that a voltage of .

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks and provide an output circuit with reduced power supply induced noise.

[Means to solve the problem]

The configuration of the output circuit of the present invention is such that the input of the first inverter is connected to the input terminal, the pressure is connected to the input of the first pre-buffer which is a delay buffer, and the output of the first pre-buffer is cascaded. A first output buffer is configured of a connected P-channel transistor and an N-channel transistor, and its output is connected to the input of a first output buffer that is connected to the output terminal, and one pole of the output of the first inverter is connected to the input terminal. a gate of a first selection circuit configured to connect the other pole of the N-channel transistor connected to the output of the first output buffer and the other pole of the P-channel transistor connected to the output of the first output buffer; , and output by connecting the other pole of the P-channel transistor whose one pole is similarly connected to the input terminal and the other pole of the N-channel transistor whose one pole is connected to the pressure of the first output buffer. is input to the gate of a second selection circuit configured to The output of the second inverter is connected to at least one or more third inverters, the output of the second inverter is connected to the input of at least one P-channel transistor connected in cascade, and the output of the third inverter is connected to the input of the N-channel transistor. It is characterized in that the output of the second pressure buffer configured by connecting the outputs is connected to the output terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing voltage waveforms at various parts in FIG. 1. 1 and 2, the present embodiment includes a first inverter 1, a first pre-buffer 2, a first output buffer 15, first and second selection circuits 21 and 22, Second. It includes a third inverter 16, 17 and a second output buffer 23. Here, the first output buffer consists of P and N channel transistors 3 and 4 connected in series. The first selection circuit 21 consists of N, P channel transistors 5, 6, the second selection circuit 22 consists of N, P channel transistors 7.8, and the second inverter 16.
are P and N channel transistors9. The third inverter 17 consists of P, N channel transistors 11.12, and the second output buffer 23 consists of P, N channel transistors 11.12.
It consists of N-channel transistors 13 and 14. Input■1
is applied, the output Vout is output, and the capacitance Ct
, is loaded.

When Vl is at the GND potential, input v1 is on the high potential side,
1st. N-channel transistors 5, 7 of second selection circuit 21.22 are in an on state, and P-channel transistor 6.8 is in an off state.

■The potential of 3 is the input ■. is at the potential of GND, which is the same potential as , and the potential of
It has a potential. The pressure (4) of the second inverter 16 is on the high potential side, and the P-channel transistor 13, which has a large current supply capability, is in an off state. V6, which is the output of the third inverter 17, is on the high potential side, and the N-channel transistor 14, which has a large current supply capability, is in an on state. Inverter 15 with low current supply capacity is connected to GND
It has a potential.

Next, when ■1 is input with a rising waveform from the GND potential to the high potential side, input ■. changes from high potential to GNDtE level. N-channel transistor 5.7 is turned off, P-channel transistor 8 is turned on, and P
The channel transistor 6 has Vout higher than V3, and the threshold voltage of the transistor 6 v1. It remains off until it goes high. The potential of v3 remains at the GND side potential until the buffer 2 with a large delay time switches the output inverter 15. (2) is also on the high potential side, and the P-channel transistor 13 also remains in the off state. ■The potential of 5 changes to the high potential side, which is the potential of input v1, and
changes to GND potential, and the N-channel transistor 14
is turned off. Here, the output of the buffer 2 switches from the high potential side to the GND potential side, and the inverter 15
13 with large current supply capacity until switching
Both the P-channel transistor 13 and the N-channel transistor 14 are in an off state. When the 8 power of the inverter 2 switches and changes from the high potential side to the GND potential, switching of the inverter 15 occurs. The N-channel transistor 4 changes from the on state to the off state, the P channel transistor 3 changes from the off state to the on state, and the output V out changes from the GND potential to the high potential side. At this time, since the current supply capability of the P-channel transistor 3 and the N-channel transistor 4 is small, the through current is also small and the noise of the power supply is small.

The N-channel transistor 4 is in the off state, the P-channel transistor 3 is in the on state, and current is supplied to the external load capacitor CL. ? When the potential becomes higher, the P-channel transistor 6 turns on, and when the potential of 13 is turned on. Although the current supply capability of the P-channel transistor 13 is large, the potential difference between the source, which is on the high potential side, and the drain, which is at the same potential as the output Vout, is lower by VT3, so that no sudden current supply is performed. The potential of v3 eventually becomes the same potential as the potential on the high potential side.

At this time, the current supply capability is the sum of P channel transistor 3 and P channel transistor 13.

Similarly, only the operations of the output transistor 13, the P-channel transistor 14, the N-channel transistor 3, etc. when a falling waveform of Vl from the high potential side to the GND potential side is input will be described.

When the input Vr is on the high potential side, the P channel transistor 13
and P-channel transistor 3 are in the on state, and N-channel transistor 14 and N-channel transistor 4 are in the off state. Vout is on the high potential side due to P channel transistors 13 and 3. Input V1 is GN
By changing to the D potential, the P channel transistor 13 is turned off. When the inverter 15 switches, the potential of the output Vout is shifted from the high potential side to the GND side by the N-channel transistor 4. Output V
The potential of V7.out is the input threshold voltage of the inverter 17. When the current is reached, the N-channel transistor 14 turns on and supplies current.

At this time, in the circuit described in the conventional technique, the GND noise is 300 mV, and the noise waveform is shown in FIG. In this embodiment, the voltage is 100 mV, and the noise waveform is shown in FIG. Compared to the conventional technology, this embodiment generates only 1/3 the noise. This is based on the results of a simulation, when the external load L is 00 pF, the GND inductance is 70 nH, and the power supply voltage is 5 V.

FIG. 3 shows a circuit diagram of another embodiment of the invention.

In FIG. 3, this embodiment differs from the embodiment shown in FIG. 1 in the configuration of the selection circuit.

The selection circuits 30 and 31 of this embodiment are configured with transfer gates 35, 36, 37, and 38, and the inputs of the transfer gates 35, 36, 37, and 38 are input signals vr and vl.

Therefore, in the embodiment shown in FIG. 3, the transfer gates 35, 36, 37, and 38 are turned on by the potentials of the inputs vr and Vl, and in the embodiment shown in FIG.
The problem that P-channel transistor 6 does not turn on unless the potential difference between P-channel transistor 6 and V reaches the threshold voltage of P-channel transistor 6 has been improved.

〔Effect of the invention〕

As explained above, the present invention senses that the output level has become an intermediate potential, and supplies current from the intermediate potential using an output transistor with a large drive capacity. Therefore, the induced voltage V (=Ld i/d
Reducing - of t) has the effect of reducing power supply noise.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an output circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. 4 is a circuit diagram of a conventional example. The circuit diagram, FIG. 5, is a timing diagram of FIG. ■...First inverter, 2...First
Pre-buffer, 3, 6. 8. 9, 11, 13...
・・P channel transistor, 4, 5, 7, 10, 12
, 14... N-channel transistor, 15...
...First output buffer, 16...Second inverter, 17...Third inverter, 21
...First selection circuit, 22...Second selection circuit, 23...Second output buffer, 30
．． 31... Selection circuit, 35, 36° 37.38
...Transfer gate. Agent: Susumu Uchihara, patent attorney Figure 2

Claims (1)

[Claims] An input of a first inverter is connected to an input terminal, an output thereof is connected to an input of a first pre-buffer which is a delay buffer, and an output of the first inverter is connected to a P-channel transistor connected in cascade. A channel transistor is connected to the input of a first output buffer whose output is connected to the output terminal, and an N-channel transistor whose output is connected to the input terminal and whose output is connected to the input terminal. and one pole are input to the gate of a first selection circuit configured to output by connecting the other pole of a P-channel transistor connected to the output of the first output buffer; P connected to the input terminal
input to the gate of a second selection circuit configured to connect the other pole of the channel transistor and the other pole of the N-channel transistor whose one pole is connected to the output of the first output buffer to provide an output; connected to the input of at least one second inverter of the output of the first selection circuit,
The output of the second selection circuit is connected to at least one or more third inverters, the output of the second inverter is connected to the input of at least one or more cascade-connected P-channel transistors, and the output of the second inverter is connected to an N-channel transistor. An output circuit characterized in that the output of a second output buffer configured by connecting the output of the third inverter to the input of the output circuit is connected to the output terminal.