JPH04172016A - Level converter - Google Patents

Abstract

PURPOSE:To reduce the error of both threshold voltages by making the transconductance ratio of the P channel transistor of a first logical element to the N channel transistor of the first logical element different from that of a second logical channel. CONSTITUTION:The transconductance ratio of the inside Pch-Tr to the Nch-Tr of an inverter 4 at the first stage is made different from that of an inverter 5 at the second stage. That is, the output direct current voltage of the inverter 4 at the first stage is made different from the threshold voltage of the inverter 5 at the second stage by making the transconductance ratio different from each other, and this device is difficult to be affected by a noise at the time of a non-signal. Thus, a level converter in which the manufacturing variance of the difference between the output direct current voltage of the inverter at the first stage and the threshold voltage of the inverter at the second stage can be reduced, can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level converter that amplifies a minute input signal of a semiconductor integrated circuit.

[Conventional technology]

FIG. 5 is a diagram showing a conventional level converter.

In the figure, l is an input terminal, 2 is a capacitor that blocks the DC component of the input signal, 4 is an inverter that amplifies the input logic signal and inverts the logic, and 3 is this inverter 4.
5 is an inverter that amplifies the output logic signal of the inverter 4 to a logic level, inverts the logic and outputs it, and 6 is a pulldown that prevents noise when there is no input signal. It is resistance.

Next, the operation will be explained. FIG. 6 is a diagram representing FIG. 5 at a transistor level. In this figure, the same parts as in FIG. 5 are given the same reference numerals.

4c and 4d are a P-channel MoS transistor (hereinafter referred to as Pch-Tr) and an N-channel MOS transistor (hereinafter referred to as Nc), which constitute the inverter 4 in FIG.
h-Tr), 5c, and 5d are Pch-Tr and Nch-Tr, respectively, which constitute the inverter 5 in FIG. The output of the inverter 4 is fed back to the input via the resistor 3. This input signal is Pch-Tr4c of inverter 4.
.

Since it is connected to the gate of the Nch-Tr 4d and the capacitor 2, no direct current flows through the resistor 3, and the input and output of the inverter 4 have the same potential. Since inverters 4 and 5 are composed of MOSh transistors of the same size, their respective threshold voltages vth
, and Pch-Tr4c, 5c, Nch-Tr4d, 5
Each transconductance gmp r of d
gmN is the same value, resistor 6 is R1, power supply voltage is Vt+
If a is the output DC voltage v4 of the inverter 4, it is given by the following equation.

V, =V th-4V, ・(1)△V2 #Vo
o/ (1+ gm, R2) −(21 above formula (2)
ΔV2 is a minute DC voltage.

A minute logic signal inputted from the input terminal 1 is removed with a DC component by a capacitor 2, and inputted into the input terminal 4 instantly as a logic signal to be amplified with reference to V4. The relationship between the human output of inverter 4 is as shown in Figure 7,
The minute logic signal amplified with v4 as a reference is logically inverted and amplified and output. The logic signal output from the inverter 4 is logically inverted with respect to vth.
A logic signal at a logic level is obtained by inputting the signal into the signal generator and amplifying it.

In addition, when there is no input signal, if noise is mixed in, the noise is amplified by the inverter 4 by the same operation as described above, but the magnitude of the noise after amplification is usually smaller than ΔV2, and v
th is not exceeded, and the output of the inverter 5 is always "H".

However, Δv2 is a signal such that the logic signal amplified by the inverter 4 exceeds vth, and the noise does not exceed vth.

[Problem to be solved by the invention]

Since the conventional level converter is configured as described above, ΔV2 in equation (2) depends on the transconductance gmp of the Pch-Tr of the inverter 4 and the value of the pull-down resistor 6, and these values are determined by this level converter. When manufacturing vessels, there are variations without correlation, and the error of Δv2 becomes large.

Therefore, when Δv2 becomes large, even if the input minute logic signal is amplified by the inverter 4, the maximum value or vt
h, and no signal appears at the output of the inverter 5; conversely, ΔV2 is small and noise mixed in when there is no signal is amplified by the inverter 4, and becomes larger than vth, and noise appears at the output of the inverter 5. There were some problems.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce manufacturing variations in the difference between the output DC voltage of the first stage inverter and the threshold voltage of the second stage inverter. The purpose is to obtain a converter.

[Means to solve the problem]

The level converter according to the present invention has Pch-Tr of internal transistors of a first stage inverter and a second stage inverter.
The transconductance ratio between the Nch-Tr and the Nch-Tr is changed.

[Effect]

In the level converter of this invention, the output DC voltage of the first stage inverter and the threshold voltage of the second stage inverter can be adjusted by changing the transconductance ratio without connecting the pull-down resistor used in the conventional type. This makes it less susceptible to noise when there is no signal.

〔Example〕 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a level converter according to an embodiment of the present invention. FIG. 2 is a diagram representing FIG. 1 at a transistor level. In both FIGS. 1 and 2, the same or corresponding parts as in FIGS. 5 and 6 are given the same reference numerals. 4a in FIG.

4b are Pch-Trs each constituting the inverter 4;
Nch-Tr, 5a and 5b are Pch-Tr and Nch-Tr constituting the inverter 5, respectively.

Next, the operation will be explained. The output of the inverter 4 is fed back to the input via the resistor 3, and this input point is connected to the gates of the Pch-Tr 4a and Nch-Tr 4b of the inverter 4 and the capacitor 2, so no DC current flows through the resistor 3. First, the input and output of the inverter 4 have the same potential. Pch-Tr4a, Nch-Tr4 of inverter 4
The transconductance and threshold voltage of b are gmp*, gmsa, and V th 1, respectively.
Then, the output DC voltage V4 of the inverter 4 is V t
h Since it changes in the vicinity of I, it is approximately given by the following formula.

In this equation (3), for example, gmp4=2.2 mQ, gmN
When i=2°8 mQ and Voo=5V, it becomes.

In addition, the Pch-Tr5a and Nch-Tr of the inverter 5
When the transconductance and threshold voltage of 5b are respectively gmps+gmsi+V th2, its output DC voltage Vth2 is given by the following equations.

In this equation (4), as an example, gm□=1.5mυ, g
If mns=1.5 mQ and Vob=5V, then.

As in the example above, V th + , V th ht
The value of is set so that Vth+ <Vth, and Δv
1=V t h t V t h + .

The DC component of the minute logic signal input from the input terminal 1 is removed by the capacitor 2, and the signal is input to the inverter 4 as a logic signal whose amplitude is based on v4.

As shown in FIG. 3, the inverter 4 has an input/output characteristic in which the logic is inverted at V th l, and a minute logic signal whose amplitude is based on v4 is logic inverted and amplified and output. The logic signal output from the inverter 4 is then input to the inverter 5, which has an input/output characteristic of logic inversion at V th z, as shown in FIG. 4, and is amplified to obtain a logic signal at a logic level.

In addition, when there is no input signal, if noise is mixed in, the noise is also amplified by the inverter 4 as described above, but V
Since t h+ <V th ht is set, the noise amplified by the inverter 4 does not exceed the value of V tht, and the output of the inverter 5 is always "H".

However, Δv1 needs to be set so that the logic signal amplified by the inverter 4 exceeds Vth, and the noise does not exceed Vthz. It is desirable to set it to 0.2 V or more, which is above the range.

〔Effect of the invention〕

As described above, according to the level converter according to the present invention, the level converter is constituted by an inverter having a threshold voltage as expressed by equations (3) and (4), that is, the P of the first logic element is Since the transconductance ratio of the channel transistor and the N-channel transistor is changed from that of the second logic channel, gmP, gmps+gmsa, and gmN are generated in the semiconductor integrated circuit.
Since s has a correlation and shows values with the same tendency, Vth
, and V th 2 vary with the same tendency, which has the effect of reducing the error in ΔV1.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a level converter according to an embodiment of the present invention, FIG. 2 is a diagram representing FIG. 1 at a transistor level, and FIG. 3 is an input/output diagram of the first stage inverter shown in FIG. Figure 4 is a diagram showing the input/output characteristics of the second stage inverter in Figure 1, Figure 5 is a diagram showing the configuration of a conventional level converter, and Figure 6 is a diagram showing the configuration of Figure 5 at the transistor level. FIG. 7 is a diagram showing the input/output characteristics of the first stage inverter shown in FIG. In FIG. 1, 4 is a first logic element, 5 is a second logic element, 3 is a resistor, 2 is a capacitor, and 4c. 5c is a P-channel transistor, and 5c and 5d are N-channel transistors. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) It has at least two or more complementary MOS logic elements, the first logic element is an inverting logic element, and a resistor is connected between the input and output of the first logic element, and the A level converter in which one end of a capacitor is connected to the connection point between the input of the first logic element and the above-mentioned resistor, and the input of the second logic element is connected to the connection point between the output of the above-mentioned logic element and the above-mentioned resistor. In, the transconductance ratio of the P-channel transistor and the N-channel transistor of the first logic element is different from that of the second logic element, and the logical threshold voltage of the first logic element and the second logic A level converter characterized in that a difference in logical threshold voltages of elements is at least 0.2V or more.