JPH04172814A - Clock discontinuation detection circuit - Google Patents

Abstract

PURPOSE:To enable the title circuit to detect clock discontinuation even when a clock input terminal is at a high or low level and, at the same time, to easily integrate the circuit by comparing a 1st clock pulse with a 2nd clock pulse through two FF circuits after dividing the 1st clock pulse into 1/2 periods. CONSTITUTION:The clock pulse (CLK) inputted to an input terminal 1 is divided to the 1/2 frequency of the CLK inputted to another input terminal 2 by means of a frequency divider 4. The divided CLK is inputted to an FF circuit 5 and the reverse phase signal of the CLK by means of the CLK of the terminal is inputted to another FF circuit 6. The normal phase output of the circuit 6 is obtained by delaying the reverse phase output of the circuit 5 by the half period and the normal phase output of the circuit 5 always coincides with the normal phase output of the circuit 6. When the input from the terminal 1 is discontinued and becomes a high or low level, the levels of the normal phase outputs of the circuits 5 and 6 do not become the same. Therefore, the clock discontinuation can be detected by discriminating the leading edge of the CLK of the terminal 2 by means of a comparator and this clock discontinuation detection circuit can easily be integrated.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a clock interruption detection circuit.

[Conventional technology]

Conventionally, this type of clock interruption detection circuit has been constructed as shown in FIG. 2. FIG. 2 is a circuit diagram showing an example of the conventional technology. In the figure, 1 is a clock input terminal, 3 is an output terminal, 1 is a clock input terminal, and 3 is an output terminal.
1 is a diode, 12 is a capacitor, 13 is a resistor, and 14 is an inverter. The clock input terminal 1 is connected to the anode terminal of the diode 11, and the cathode terminal of the diode 11 is connected to the capacitor 12, the resistor 13, and the inverter. 14 input terminals. The other terminals of the capacitor 12 and resistor 13 are connected to the earth 15,
The output of inverter 14 is connected to output terminal 3.

If there is a clock input to input terminal 1, capacitor 10
A charging current flows through, the input of the inverter 14 becomes high level, and a high level is also output to the output terminal 3. When input terminal 1 becomes low level, capacitor 12 is discharged and the input of inverter 14 becomes low level, output terminal 3 becomes low level.
A low level is also output. i.e. capacitor] −
A pulse interval longer than a certain time width of the second discharge time is confirmed at the output terminal as a clock interruption.

[Problem to be solved by the invention]

The conventional clock loss detection circuit described above has a configuration that uses a CR filter, so the capacitor and resistor are large, making it unsuitable for integration into an IC (integrated circuit). The problem was that it could only detect cases.

An object of the present invention is to provide a clock disconnection detection circuit that solves the above problems.

[Means to solve the problem]

The clock disconnection detection circuit of the present invention inputs a first clock pulse, converts it into a 1/2 period, outputs the divided period, and connects the output of this divided period as a data input and the second clock pulse as a clock input. a first flip-flop circuit; a second flip-flop circuit connected to the opposite-phase output of the first flip-flop circuit as a data input and a second clock pulse as a clock input; and a comparator that inputs the outputs of the respective clock pulses, compares them at the rising edge of the second clock pulse, and outputs a determination.

〔Example〕

Next, the present invention will be explained with reference to FIG.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, this clock disconnection detection circuit is composed of a dividing period 4, a flip-flop circuit (F/F) 5.6, and a comparator 7.

The illustrated clock disconnection detection circuit connects the input of the divided period 4 to the input terminal 1 which is the first clock input terminal, and connects the output to the data input terminal of the F/F circuit 5 which is the first F/F circuit. The reverse phase output of F/F circuit 5 is connected to the data input terminal of F/F circuit 6, which is the second F/F circuit, and the F/F circuit 5 is connected to
F times#! The positive phase output of F/F circuit 5 and the positive phase output of F/F circuit 6 are connected to the input terminal of comparator 7. Furthermore, the clock loss detection circuit connects the output of the comparator 7 to the output terminal 3, and connects the clock input terminals of the F/F circuits 5, 6 and the comparator 7 to an input terminal that is a second clock input terminal.

The clock pulse inputted to the input terminal 1 is divided by the frequency divider 4 to half the frequency of the clock pulse inputted to the input terminal 2. This divided clock pulse is F
Of the positive phase and negative phase signals formed by the clock pulses input to the /F circuit 5 and input to the input terminal 2, the reverse phase signal is input to the F/F circuit 6 and input to the input terminal 2. The signal delayed by one clock of the clock pulse sent to the F/F
It is output from the positive phase output of the circuit 6. Since the output of the F/F circuit 6 has a frequency that is half the frequency of the clock pulse input to the input terminal 2, the positive phase output of the F/F circuit 6 is equal to the negative phase output of the F/F circuit 5. This is a signal delayed by half a cycle of the output of the /F circuit 5. Therefore, the positive phase output of F/F circuit 5 and P/
Since it always matches the positive phase output of F circuit 6, by inputting these two signals to comparator 7 and making a decision at the rising edge of the clock pulse at input terminal 2, the output of comparator 7 becomes high level. Become.

When the input from the input terminal 1 is cut off and becomes either high or low level, the positive phase outputs of the F/F circuits 5 and 6 will never be at the same level. Therefore, the output of comparator 7 becomes low level.

Therefore, when a clock pulse is input to the first clock input terminal 1, a high level is output to the output terminal,
When no clock pulse is input, a low level can be output to the output terminal regardless of whether the first clock input terminal l is high or low.

〔Effect of the invention〕

As explained above, the present invention connects the divided period input to the first clock input terminal, connects the output to the input of the first F/F circuit, and outputs the negative phase output of the first F/F circuit. to the second F/
Connect to the input of the F circuit, connect the positive phase output of the first F/F circuit and the positive phase output of the second F/F circuit to the input of the comparator, and connect the output of the comparator to the output terminal. In addition, 1. By connecting the clock input terminal of the second F/F circuit and the comparator to the second clock input terminal, a high level is output to the output terminal when a clock pulse is input to the first clock input terminal. When no clock pulse is input, the circuit can be configured with an integrated circuit that outputs a low level to the output terminal regardless of whether the first clock input terminal is high or low.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the clock disconnection detection circuit of the present invention, and FIG. 2 is a circuit diagram showing an example of the conventional technology. 1.2... Input terminal, 3... Output terminal, 4... Frequency divider, 5, 6... Flip-flop (F/F) circuit,
7... Comparator.

Claims (1)

[Claims] The first clock pulse is input and converted into a 1/2 cycle and output, and the output of this divided cycle is used as the data input for the second clock pulse.
a first flip-flop circuit to which the clock pulse of the first flip-flop circuit is connected as a clock input; and a second flip-flop circuit to which the reverse phase output of the first flip-flop circuit is connected as a data input and a second clock pulse is connected as a clock input. and a comparator that inputs the outputs of the first and second flip-flop circuits, compares them at the rising edge of the second clock pulse, and outputs a determination.