JPH04181599A - Digital integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a digital integrated circuit used as a control system for a drive circuit for a thermal head of a printer, an LED (light emitting diode) display device, an LCD (liquid crystal display), etc. In particular, the present invention relates to the configuration of a digital integrated circuit having a dynamic shift register circuit and a latch circuit that holds the output potential of the dynamic shift register circuit.

[Conventional technology]

Conventionally, a general multi-output drive circuit, as shown in Fig. 3,
Serial data signal Si based on clock signal CLK
a shift register 100 that converts n-bit parallel data signals Q1 to Ql, a latch circuit 200 that stores and holds each of the data signals Q1 to Q based on the latch signal, and an output signal RI of the latch circuit 200. ””
R- controlled by the high current or high voltage output P. I
``'' An output circuit 300 forming a P on.

This shift register circuit 100 includes a static type that includes a feedback circuit for data retention within the circuit, and a dynamic type that retains data using parasitic capacitance within the circuit. Static shift register circuits have an internal feedback circuit for data retention, so they have a high data retention capacity, but when configuring a multi-bit circuit, each bit has a large number of components, so the area it occupies is limited. becomes large. In particular, when displaying gradations (for example, 4 to 16 gradations) on an LCD display, the number of bits that is twice the number of gradations of a conventional shift register is required, and the expansion of the area occupied by the integrated circuit It also greatly affects the overall size of the

Therefore, if data retention for a short period of time is generally sufficient,
Typically, a dynamic shift register circuit is used. In this dynamic shift register circuit, as shown in FIG. 4, the circuit configuration for one bit is composed of transfer gate 1, inverter 3, transfer gate 5, and inverter 7, and transfer gates 1 and 3 are , are designed to open and close alternately based on a clock signal. During the period when the clock signal is at H level, the transfer gate 1 is conductive, so a data signal is taken in from the input section and an inverted signal is outputted from the inverter 3. When the clock signal becomes L level in this state, transfer gate 1 is cut off and transfer gate 5 is made conductive, so that the inverted signal output from inverter 3 is again inverted by inverter 7 and output from output section Q.

In this circuit, there is a parasitic capacitance inside the circuit! 21 and 22, the internal potential is temporarily held constant within the time corresponding to the pulse width of the clock signal, and a feedback circuit is not required. When formed as part of an integrated circuit, a multi-bit circuit can be formed with a small footprint.

Further, FIG. 5 shows the constituent parts for one bit of the latch circuit. In this latch circuit, the output Q of the shift register circuit is connected to the input P, and the latch signal LA
Transfer gates 11 and 12 are opened and closed alternately based on TCH, and when transfer gate 11 is in a conductive state, a signal applied to input P is inverted by inverter 13 and appears at output R. ,
When the transfer gate 12 is in a conductive state,
The inverter 14 performs a feedback operation based on the signal value that has already been input to maintain the circuit in a constant state and hold the potential appearing at the output R.

[Problem to be solved by the invention]

However, the conventional shift register circuit described above has the following problems.

In other words, when the shift register circuit is operated by a clock signal with a normal cycle, the data retention capacity due to the parasitic capacitance 21, 22 does not cause any problems, but when adjusting the gradation of the display or detecting leakage current, etc. In some cases, measurement is performed by lowering the frequency of the clock signal. In this case, a longer data retention time than usual is required, so the leakage current causes the accumulated charge in the parasitic capacitance to be discharged, and the data signal is The problem arises that the value of changes.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and its object is to reduce the area occupied by the circuit by providing a feedback circuit consisting of a part of another circuit configuration in the data holding section of a dynamic shift register. without increasing
An object of the present invention is to provide a digital integrated circuit having data retention capability similar to that of a static type.

[Means to solve the problem]

In order to solve the above problems, first switching means, such as a MOSFET, which is to be opened and closed based on a clock signal,
ET, etc., and a dynamic shift register circuit including a first potential holding section that temporarily holds the potential input through the first switching means, and a second shift register circuit that opens and closes based on a latch signal. has a switching means,
a latch circuit including a second potential holding section that inputs the output value of the dynamic shift register circuit through the second switching means and holds the potential for a predetermined time;
In a digital integrated circuit equipped with a digital integrated circuit, the means taken by the present invention includes a third switching means to be opened and closed based on a control signal, and the potential of the second potential holding section is changed to a second potential through the third switching means. A feedback circuit is provided to transmit the information to the first potential holding section. Here, the first to third switching means are transfer gates, and the first potential holding section and the second potential holding section may each include an inverter circuit.

In addition, an output circuit that uses the output of the launch circuit as a control signal, such as a high voltage output circuit, is added to the digital integrated circuit described above.
A current output circuit and the like are provided to form a multi-output drive integrated circuit.

[Effect]

According to this means, when the shift register circuit is operated based on a low-frequency clock signal, the third switching means is made conductive to transfer the voltage from the second potential holding section to the first potential holding section. Since the feedback circuit that transmits the potential is connected to the shift register circuit, and the shift register circuit has a circuit configuration similar to that of a static type, its potential holding ability is improved. In other words, the period during which the shift register circuit needs to hold the potential occurs every cycle of the clock signal, but as a digital circuit, the output of the shift register circuit is held at a constant value only during the period when the next-stage latch circuit takes in the signal. Since the second switching means is always in a conductive state during this period, as long as the third switching means is in a conductive state, the first potential holding part, the second potential holding part, and the second switching means are in a conducting state. Since a potential transmission feedback loop consisting of a feedback circuit is formed, the potential is held constant.

Therefore, the digital circuit can be reliably operated without causing potential changes due to leakage current.

Compared to conventional circuits, this circuit only needs to newly install a third switching means for switching the circuit configuration, and the feedback circuit itself can use the latch circuit components as they are. The increase in occupied area can be minimized.

〔Example〕

The present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a dynamic shift register circuit S and a latch circuit T whose output Q is an input P. The shift register circuit S has transfer gates 1 and 5 and an inverter 3. A potential holding section consisting of an inverter 3 is provided between the gate 1 and the transfer gate 50, and a potential holding section consisting of an inverter 7 is provided on the output side of the transfer gate 5, and each potential holding section is composed of one inverter. Does not have a feedback circuit. On the other hand, the latch circuit T has the transfer gate 1
1 and 12 and inverters 13 and 14, and the potential holding section equipped with the inverter 13 has a transfer gate 12.
A feedback circuit consisting of an inverter 4 and an inverter 4 is provided.
It enables long-term data retention.

In this embodiment, the inverter 7 of the shift register circuit S
The input side of the latch circuit T and the output side of the inverter 13 of the latch circuit T are connected via a transfer gate 15,
The transfer gate 15 is alternately opened and closed relative to the transfer gate 5.

Next, the operation of this circuit will be explained. When a data signal is applied to the input of the shift register S, this data signal is taken in by the closing of the transfer gate 1 controlled by the clock signal C, and the inverted signal by the inverter 3 is alternately connected to the transfer gate 1. The data signal is inputted to the inverter 7 via the transfer gate 5 which opens and closes, and the data signal is inverted again and given to the output Q.

Here, when the transfer gate 5 is open,
As shown in FIG. 2, the transfer gate 15 is closed and the feedback circuit connecting the input side of the inverter 7 and the output side of the inverter 13 becomes conductive.

When the transfer gate 11 is closed by the latch signal in this state, the inverter 7, the transfer gate 11, the inverter 13, and the transfer gate 1
A feedback loop consisting of 5 is formed, and a potential holding section similar to the static type appears. Therefore, since the output potential of the shift register S is held constant, the function as a digital circuit is not impaired even when the frequency of the clock signal is low.

In this state, after the data signal has been taken into the latch circuit T, and after the transfer gate 11 is opened and the transfer gate 12 is closed, the latch circuit T is configured to consist of an inverter 13, an inverter 14, and a transfer gate 12, as in the conventional latch circuit. A feedback loop is formed and the data is retained.

In this way, in this embodiment, the transfer gate 15
Dynamic shift register S can be installed without increasing the area occupied by the circuit by simply installing
The data retention capacity of the static type can be increased to the same extent as the static type. In this case, as described in the above description of the operation, even when the feedback circuit having the transfer gate 15 is operated, the function as a conventional latch circuit is not impaired in any way.

In the above embodiment, transfer gate 15 is controlled by a clock signal like transfer gates 1 and 5, but normally transfer gate 15 is shut off and the frequency of the clock signal is lowered during gradation adjustment or leak detection. Transfer gate 15 only if
It is also possible to operate Further, the transfer gate 15 can also be controlled by a latch signal.

Each of the above transfer gates can use a MOSFET, a bipolar transistor, or another switching element, and in each inverter, a MOSFET, a bipolar transistor, or another switching element can be used.
Various circuits including an S inverter can be used.

〔Effect of the invention〕

As described above, the present invention provides a digital integrated circuit that includes a dynamic shift register and a latch circuit, in which a first potential holding section of the shift register and a second potential holding section of the latch circuit are connected to each other. Since the feature is that a feedback circuit equipped with the switching means 3 is provided, the potential holding ability of the shift register can be improved without substantially increasing the area occupied by the circuit, and the clock signal frequency of the shift register can be increased. Even when the signal value is lowered, changes in the level of the signal value can be suppressed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment according to the present invention. FIG. 2 is a circuit diagram showing the configuration of a portion functioning as a shift register in the same embodiment. FIG. 3 is a block diagram showing the overall configuration of the multi-output driving integrated circuit. FIG. 4 is a circuit diagram showing the configuration of a conventional dynamic shift register. FIG. 5 is a circuit diagram showing the configuration of a conventional latch circuit. [Explanation of symbols] S...Shift register circuit T...Latch circuit C...Clock signal L...Latch signal 1.5, 11, 12.15...Transfer gate Fig. 1 Fig. 2 Figure 6 Figure 4 Figure 5

Claims (3)

[Claims] (1) A dynamic shift register having a first switching means that opens and closes based on a clock signal, and a first potential holding section that temporarily holds the potential input through the first switching means. circuit, and a second switching means to be opened and closed based on a latch signal, through which the output value of the dynamic shift register circuit is input, and the potential thereof is to be held for a predetermined period of time. a latch circuit equipped with a potential holding section; and a digital integrated circuit comprising a third switching means to be opened and closed based on a control signal, and the second potential holding section is connected to the second potential holding section through the third switching means. A digital integrated circuit comprising: a feedback circuit for transmitting the potential of the first potential to the first potential holding section. (2) In the digital integrated circuit according to claim 1, the first to third switching means are transfer gates, and the first potential holding section and the second
A digital integrated circuit characterized in that each of the potential holding parts has an inverter circuit. (3) A multi-output drive integrated circuit comprising the digital integrated circuit according to claim 1 or 2, and an output circuit that uses the output of the latch circuit as a control signal.