JPH04181742A - Field effect transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To enhance the speed of carriers without lowering a draingate breakdown strength by a method wherein the resistance of only a source formation region is made low and a gate electrode is formed in such a way that its cross section is T-shaped. CONSTITUTION:An active layer 1a is formed near the surface of a semiinsulating GaAs substrate 1; the resistance of a source formation region 1s is made low; a source electrode S is formed on the surface of the source formation region 1s so as to come into ohmic contact with the GaAs substrate 1. A drain electrode D is formed on the surface of a drain formation region 1d so as to come into ohmic contact with the GaAs substrate 1. A gate electrode G is formed on a gate formation region 1g situated on the side of the source formation region 1s in such a way that its cross section is T-shaped in the direction of a gate length; an SiN film 2 is formed between the gate electrode G, the source electrode S and the drain electrode D. In this manner, the resistance of only the source formation region 1s is made low. Thereby, the speed of carriers can be enhanced without lowering a drain-gate breakdown strength.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to field effect transistors, particularly for high frequency operation used in microwave integrated circuits (MIC) and monolithic microwave integrated circuits (M old C). The present invention relates to a field effect transistor and a method for manufacturing the same.

[Conventional technology]

MICs and MMICs made of GaAs and intended for high frequency operation in the microwave band are constructed by combining active elements such as field effect transistors and passive elements such as resistors and capacitors. Is the operating frequency of MIC or MMIC 2?
Since t: is very high, such as C: H2 or more, the field effect transistor used here is required to have high speed.

Therefore, the current cutoff frequency (f
Various efforts have been made to improve T).

Specifically, in order to improve the transconductance (g) and reduce the gate capacitance, we will use a short submicron gate, and in order to reduce the source resistance, we will implant ions using a T-shaped dummy gate as a mask. By doing this, the resistance of the source formation region and the drain formation region is lowered in a self-aligned manner with respect to the gate electrode.

Further, a high electron mobility transistor (IIEMT) in which an active layer and a low resistance layer are formed by epitaxial growth and a gate formation region has a recessed structure has been used.

[Invention or problem to be solved]

However, if the source formation region and the drain formation head which are located symmetrically on both sides of the gate electrode are made to have low resistance by using a dummy gate, the low resistance region on the source side becomes self-aligned with the gate electrode. Although it is desirable that the low resistance region is formed close to the gate electrode to reduce the source resistance, at the same time, the low resistance region on the drain side is also formed close to the gate electrode, which deteriorates the 1-■ characteristics and reduces the drain conductance (
g d) or get worse. In particular, because the gate-drain breakdown voltage is low, it cannot be used in power PETs that operate in a high frequency region and flow large currents.

Further, if a recessed structure is used, there is a problem that the uniformity of the device is impaired and the yield is reduced.

Therefore, an object of the present invention is to provide a field effect transistor with a high f□ that operates in a high frequency region without reducing the yield.

In addition, a gate electrode with a short gate length can be easily formed, and fr
An object of the present invention is to provide a manufacturing method that can manufacture a field effect transistor with high performance.

[Means to solve the problem]

In order to solve the above object, the present invention has a gate electrode formed in a T-shaped cross section in the gate length direction on a semiconductor substrate, and a low resistance layer formed in a self-aligned manner only in the source formation region of the semiconductor substrate. It is equipped with

Further, the step of exposing the gate formation region and the source formation region of the semiconductor substrate to form a first mask member, and covering the first mask member with a second mask member;
By etching back the mask member, the second mask member on the source formation region is removed, and the second mask member attached to the side wall of the first mask member is left to form the gate. forming a dummy gate on the region; forming a low resistance region in the source formation region by injecting impurities into the semiconductor substrate in self-alignment with the dummy gate; Forming a gate pattern on the dummy gate having an opening that exposes only the top of the dummy gate, and removing the dummy gate; forming a gate electrode using the opening of the gate pattern; and a step of removing the pattern.

[Effect]

According to the field effect transistor according to the present invention, only the resistance between the source and the gate decreases, and the drain gate breakdown voltage does not decrease. Therefore, the carrier speed between the source and gate is improved and high breakdown voltage is maintained.

Further, according to the method for manufacturing a field effect transistor according to the present invention, since the second mask member attached to the side wall of the first mask member on the gate formation region becomes a dummy gate, the second mask member attached to the side wall on the gate formation region of the first mask member is The gate length can be controlled by the thickness of the second mask member deposited on the gate. Therefore, if this film thickness is made submicron, a gate pattern with a submicron gate length can be formed, and a field effect transistor with a submicron gate length can be easily manufactured.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and redundant description will be omitted.

FIG. 1 is a sectional view showing the structure of a field effect transistor according to an embodiment. An active layer 1a is formed near the surface of the semi-insulating GaAs substrate 1, and a source formation region 1s
Ions are implanted into the material to lower its resistance. A source electrode S is formed on the upper surface of this source formation region 1s in ohmic contact with the GaAs substrate 1. In addition, a drain electrode layer is made of GaA on the upper surface of the drain formation region 1d.
It is formed in ohmic contact with the s-substrate 1.

The gate electrode G has a T-shaped cross section (
It is formed like a pine mushroom. A SiN film 2 is formed between this gate electrode G and the source electrode S and drain electrode.

In this way, only the source formation region 1s has a low resistance, so g and fT can be improved without reducing the drain/gate breakdown voltage.

In addition, although the insulating film (SiN film 2) is formed on the gate formation region, the gate electrode G with a wide head is formed at a higher position than the gate formation region, so that the gate capacitance C is reduced. I can do it. Furthermore, since the gate cross section is large, the gate resistance R can be reduced, resulting in excellent high frequency characteristics.

Next, a method for manufacturing a field effect transistor according to an example will be described. FIG. 2 is a process diagram showing a method for manufacturing the field effect transistor.

First, Si ions 3 are implanted onto a semi-insulating GaAs substrate 1, and then the ion implanted portion is activated by annealing to form an active layer 1a on the substrate surface. Furthermore, a SiN film 2 of, for example, 80% is coated on the surface using plasma CVD technology.
Grow to a film thickness of 0 angstroms ((a) in the same figure)
. Note that the active layer 1a may be formed by an epitaxial growth method.

Next, using photolithography technology, a resist pattern (first mask pattern) 3 having openings on the source formation region and gate formation region of the GaAs substrate 1 is formed.
．． A film with a thickness of about 0 μm is formed, and then the resist pattern 3 and the above-mentioned openings are formed using a sputtering method or E, which can perform low-temperature treatment to the extent that the resist pattern 3 is not destroyed.
A SiO2 film (second mask pattern) 4 is deposited using the CR-CVD method (FIG. 4(b)).

Thereafter, for example, by anisotropic etching from above using a gas such as CF4 by RIE, the 5IO2 attached to the sidewall of the gate formation region in the resist pattern 3 is removed.
Etch back the 5i02 film 4 so that only the film 4 remains,
A dummy gate g is formed. Next, this dummy gate g
Then, using the resist pattern 3 as a mask, Si ions are implanted obliquely from the drain side at an angle of approximately 7 to 10 degrees to form a low-resistance source region in self-alignment with the dummy gate g (Figure (C)). ). The acceleration energy of Si ions is 90keV, and the dose is 4X 1013cm.
-2 or so can be used, dummy gate g and source region 1s
The interval can be changed by changing the irradiation angle of Si ions.

After that, the unnecessary part of the dummy gate g (GaAs substrate 1
S io formed on a region other than the upper gate formation region
The implanted Si ions are activated by removing the second film 4) and the resist pattern 3 and performing annealing. Thereafter, using photolithography technology, the source electrode S and the drain electrode are formed in ohmic contact with the GaAs substrate 1, and a resist film 5 is applied again to a film thickness of about 1.5 μm ((d) in the same figure. )).

Thereafter, this resist film 5 is etched by RIE using a gas such as 02 until the top of the dummy gate g is exposed (FIG. 1(e)), and then this dummy gate g is formed using photolithography A resist pattern 6 is formed which has an opening wider than the area where the resist pattern 6 is formed (see FIG.
f)). Therefore, the head of the dummy gate g and a part of the resist film 5 are exposed in this opening.

Next, the dummy gate g is removed by wet etching using I Far F' HF, and the S I O2 film 2 under the dummy gate g is further removed (
Figure (g)). With this resist film 5 and resist pattern 6, the shape pattern of the gate electrode is completed. In this case, wet etching is used, but R
You can also use IE.

Thereafter, a gate metal consisting of Ti/Pt/Au is vacuum-deposited from above to a thickness of approximately 8000 angstroms, and the resist film 4 and resist pattern 5 are removed by lift-off, thereby forming the gate electrode G.
is formed ((h) in the same figure).

In this way, the above-mentioned field effect transistor can form a low resistance region between the source electrode S and the gate electrode G in a self-aligned manner with the dummy gate g. The distance between the gate G and the source region 1s can be set with high accuracy.

In addition, since a gate electrode having a gate length on the submicron order can be formed only by optical exposure without directly drawing on the wafer as with electron beam (EB) ff light, productivity can be improved.

Note that the present invention is not limited to the above embodiments.

For example, GaAs is used as a substrate, but
It is not limited to GaAs.

〔Effect of the invention〕

In the field effect transistor according to the present invention, only the source formation region has a low resistance and the gate electrode is formed in the shape of a mushroom. Therefore, the field effect transistor operates in a high frequency region without reducing the drain breakdown voltage of the field effect transistor, and , it is possible to provide a low-noise, high-power FET with a small gate capacitance.

Further, the method for manufacturing a field effect transistor according to the present invention can form a submicron gate in a self-aligned manner using only optical exposure, so that a field effect transistor that operates at a high frequency can be manufactured with high productivity.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal sectional view showing an example of the structure of a field effect transistor according to an embodiment of the present invention, and FIG. 2 is a process diagram showing a method for manufacturing the field effect transistor. S...source electrode, D...drain electrode, G...gate electrode, 1...GaAs substrate, 2...SiN film,
3...Resist pattern (first mask pattern),
4...S i 02 film (second mask pattern), 5
...Resist film, 6...Resist pattern agent patent attorney Yoshi horizontal direction
Mountain 1) Row - Figure 1

Claims (1)

[Claims] 1. A gate electrode having a T-shaped cross section in the gate length direction on a semiconductor substrate, and a low resistance layer formed in a self-aligned manner only in a source formation region of the semiconductor substrate. field effect transistor. 2. Forming a first mask member by exposing the gate formation region and the source formation region of the semiconductor substrate, and covering the first mask member with a second mask member; and etching the second mask member. By backing up,
removing the second mask member on the source formation region and leaving the second mask member attached to the sidewall of the first mask member to form a dummy gate on the gate formation region; , forming a low resistance region in the source formation region by injecting impurities into the semiconductor substrate in a self-aligned manner with the dummy gate; forming a gate pattern having an exposed opening on the dummy gate and removing the dummy gate; forming a gate electrode using the opening of the gate pattern and removing the gate pattern. A method of manufacturing a field effect transistor comprising: