JPH04182971A - Digital recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent errors from occurring concentrated in one error correcting block by arranging the data of the two error correcting blocks alternately, arranging error detecting codes alternately behind it, thereby constructing one synchronous block. CONSTITUTION:The data, D11, D12, D13,... and D21, D22, D23,... of the two error correcting blocks 39, 40, respectively are arranged alternately, then behind this arrangement, the error detecting codes, A11,... and A21,... are arranged alternately, to be one synchronous block 41. In this case, by means of an error transmission which is particular to NRZI modulation, the generation of errors in concentration in one error correcting block 39 or 40 can be prevented. Thus, the reduction in an error correcting capability is prevented. Also, error corrections can be performed by means of only one synchronous block, and redundancy is reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a digital recording/reproducing device such as a digital audio tape recorder, and in particular, to improve the error correction ability by improving the data arrangement thereof. It's about what you want to do.

(Prior Art) As is well known, in a digital recording and reproducing device that converts an information signal into digital data and records and reproduces it on a recording medium such as a magnetic tape, an error check code is added to the digital data at the time of recording. By performing processing and interleaving processing, and performing deinterleaving processing, error correction processing based on an error check code, etc. during reproduction, data errors accompanying recording and reproduction are improved.

In particular, in digital audio recorders, etc., the third
Data Dll and DI2. shown in FIG. D13゜・
...and error check code A11. . . . error correction block 11, and data D21. D22
．． D23°...and error check code A21.・
The error correction block 12 consisting of the synchronization signal 5YNC and the data Dll, D21.12 shown in FIG. D
12. Two sync blocks 13.14: a sync block 13 consisting of D22゜..., and a sync block 14 consisting of synchronization signal SYNC, data and error check code All, A21゜... I try to interleave and record.

By the way, in the configuration in which two specific error correction blocks 11.12 are interleaved with two sync blocks 13.14 as described above, it is not possible to perform error correction as soon as one sync block 13 or 14 is reproduced. Yes, but there is a problem with it being difficult to use in practice.

Therefore, conventionally, for example, one error correction block is
Are there any methods being considered, such as interleaving into one sync block or interleaving multiple error correction blocks into one sync block? , there is a disadvantage that the redundancy of the sync block increases, and with the latter method, error correction can be performed just by reproducing one sync block, and the redundancy of the sync block can also be reduced. Since the interval between the synchronization signals 5YNC increases, during special playback of a VTR (video tape recorder), it becomes difficult to synchronize as a pseudo synchronization signal is generated, and good data playback becomes impossible. .

In addition, NRZ is added to the sink block after interleaving processing.
I (Non ψ return φ toe zero invert)
In a device that modulates and records data, a 1-bit error at a symbol boundary appears as a 2-symbol error during reproduction, increasing the error rate. Specifically, as shown in FIG. 4(a), rOJ, r3
If there are two consecutive symbols J, if these symbols are considered to be two binary digits and recorded with NRZ I modulation, the recorded binary pattern will be r as shown in Figure (b).
oollJ, and the recording pattern on the recording medium is as shown in FIG.

During reproduction, if the reproduced signal pattern makes an error at the symbol boundary as shown in FIG. 4(d), the reproduced binary pattern obtained from this reproduced pattern will be as shown in FIG. 4(e). ro 101J, and the resulting symbols are rlJ, r
lJ, and errors will occur in two symbols.

Due to such error propagation peculiar to NRZI modulation, errors occur concentrated in one error correction block,
This leads to a decline in error correction ability.

(Problems to be Solved by the Invention) As described above, in the conventional digital recording/reproducing device, when an error correction block is made to correspond to a plurality of sync blocks, one
Even if only one sync block is reproduced, error correction cannot be performed; if one error correction block corresponds to one sync block, redundancy increases; if multiple error correction blocks correspond to one sync block, synchronization signal It has various problems such as even becoming a stag. Furthermore, conventional methods have the disadvantage that error propagation, which is unique to NRZ I modulation, tends to occur, leading to a reduction in error correction ability.

Therefore, this invention was made in consideration of the above circumstances, and solves various conventional problems when interleaving an error correction block with a sync block.
It is an object of the present invention to provide an extremely good digital recording and reproducing device that is less prone to error propagation peculiar to I modulation and can improve error correction capability.

[Structure of the Invention] (Means for Solving the Problems) A digital recording and reproducing apparatus according to the present invention includes a dividing means for dividing an input data string into predetermined error correction blocks including a plurality of data, and an output from the dividing means. an error check code addition means for adding an error check code to each error correction block; and an error check code addition means for adding error check codes to each error correction block; an interleaving means for arranging the data in an alternating manner and then arranging the error correction codes included in each block in an alternating manner; and synchronization for a set of two error correction blocks arranged into one by this interleaving means. A sync signal adding circuit that adds signals to form one sync block, a recording/reproducing means for recording and reproducing the sync block outputted from the sync signal adding circuit onto a recording medium, and a sync block reproduced by the recording/reproducing means. removal means for removing a synchronization signal from the block; deinterleaving means for dividing data output from the removal means into two error correction blocks; The apparatus is equipped with an error correction means for performing error correction processing using the error correction means, and a conversion means for converting the error correction block outputted from the error correction means into the original input data string.

(Operation) According to the above configuration, the data of two error correction blocks are arranged alternately, and then the error check codes are arranged alternately to constitute one sync block, so NRZ Due to error propagation specific to I modulation, it is possible to prevent errors from occurring concentrated in one error correction block, and it is possible to prevent error correction performance from deteriorating. In addition, error correction can be performed using only one sync block, and redundancy can be lowered compared to conventional means in which one error correction block corresponds to one sync block. Various conventional problems when interleaving into blocks can be solved.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. In FIG. 1, 15 is an input terminal to which input data to be recorded is supplied. This input terminal 15
The input data supplied to is supplied to the correction code series formatter circuit 16 and format-converted into a predetermined error correction block.Then, the input data is supplied to the correction code series formatter circuit 16 and converted into a predetermined error correction block. , an error check code is added to each error correction block and sent to the interleaving circuit 20.

This interleaving circuit 20 performs interleaving processing by writing each error correction block to which an error check code has been added into the memory 21 and reading it out in a different order.This processing is performed by the write address generation circuit 2
The write address and the read address output from the switch 2 and the read address generation circuit 23 are sent to the switch 24.
This is done by selectively supplying the data to the memory 21 according to the data. Each interleaved error correction block is added with the synchronization signal 5YNC output from the synchronization signal generation circuit 26 by the addition circuit 25, and then NRZ I modulated by the NRZ I modulation circuit 27 and sent to the recording/reproducing system 28. and recorded on a recording medium such as a magnetic tape.

On the other hand, the data reproduced by the recording/reproducing system 28 is NR
After being supplied to the Z I demodulation circuit 29 and demodulated into NRZ 1, the synchronization signal 5YNC is removed by the synchronization signal removal circuit 30 and sent to the deinterleave circuit 31. The deinterleaving circuit 31 performs deinterleaving processing by writing each input error correction block into the memory 32 and reading it out in a different order. This is done by selectively supplying the write address and read address output from the memory 32 to the memory 32 using the switch 35. and,
Each deinterleaved error correction block is supplied to the error correction circuit 36 and subjected to error correction processing based on the error check code added to each block.
The data is supplied to the output formatter circuit 37, reconverted to the original data array, and taken out from the output terminal 38.

Here, the interleaving circuit 20 performs interleaving by changing the order of data within two specific error correction blocks. Specifically, the second
Data D11°Dl2. shown in Figure (a). Dl3.・・・
...and error check code A11. . . . error correction block 39 and data D21°D22.
D23. . . . and error check code A21.・
Consider two particular error correction blocks 39, 40 with an error correction block 40 consisting of . Then,
First, the synchronization signal generation circuit 26 outputs the synchronization signal 5YNC, and then the interleave circuit 20 outputs the data D11. D21. D12. D 22゜Dl
3. D23. . . . followed by error check codes A1.1. A21. . . . and is eventually converted into a sync block 4 as shown in FIG. In this case, the synchronization signal 5Y
Data as close as possible to NC (Dl, 1, D21, etc.)
For example, it is assumed to be relatively important information such as header information.

On the playback side, a synchronization signal removal circuit 30 outputs a synchronization signal 5YNC to the sync block 41 shown in FIG. 2(b).
is removed and converted by the deinterleave circuit 31 into two error correction blocks 39 and 40 shown in FIG.

According to the configuration of the above embodiment, first, the data Dll, D12. of the two error correction blocks 39.40.
D13. ...and D21. D22. D2
3. . . . are arranged alternately, and then error check codes A11 . ...and A21. ... are arranged alternately to form one sync block 41, so that errors are concentrated in one error correction block 39, 40 due to error propagation peculiar to NRZI modulation. This can prevent the error correction ability from deteriorating. Also, one sink block 4
Error correction can be performed with only 1, and redundancy can be lowered compared to conventional means in which one error correction block corresponds to one sync block, and when interleaving error correction blocks to a sync plotter, can solve various conventional problems. moreover,
Since important data is arranged near the synchronization signal 5YNC, errors caused by bit slips can be suppressed.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, various conventional problems when interleaving an error correction block with a sync block can be solved, and the error propagation peculiar to NRZI modulation, which tends to occur, is less likely to occur, and error correction can be achieved. It is possible to provide an extremely good digital recording/reproducing device with improved performance.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing an embodiment of a digital recording/reproducing apparatus according to the present invention, FIG. 2 is a diagram for explaining conversion from an error correction block to a sync block in the embodiment, and FIG. A diagram for explaining the conversion from a conventional error correction block to a sync block, Figure 4 is an NRZ
FIG. 3 is a diagram for explaining error propagation of I modulation. 11.12...Error correction block, 13.14...
Sync block, ]5... Input terminal, 16... Correction code series formatter circuit, ]27... Error check code generation circuit, 8... Addition circuit, 19... Error check code addition circuit, 20...Interleave circuit, 21...
・Memory, 22...Writing atris generation circuit, 23.
...Read address generation circuit, 24...switch,
25...Addition circuit, 26...Synchronization signal generation circuit, 2
7... NRZI modulation circuit, 28... Recording and reproducing system, 2
9... NRZI demodulation circuit, 30... Synchronization signal removal circuit, 31... Deinterleave circuit, 32... Memory, 33... Write atris generation circuit, 34...
Read address generation circuit, 35... switch, 36
...Error correction circuit, 37...Output formatter circuit, 38...Output terminal, 39.40...Error correction block, 41...Sink block. Applicant's agent Patent attorney Takehiko Suzue Figure 4

Claims (2)

[Claims] (1) dividing means for dividing an input data string into predetermined error correction blocks including a plurality of data; error check code adding means for adding an error check code to each error correction block output from the dividing means; This error check code adding means alternately arranges a plurality of data contained in each block for two error correction blocks to which error check codes have been added, and then alternately arranges the error correction codes contained in each block. an interleaving means for arranging the blocks in an array, a synchronous signal adding circuit for adding a synchronous signal to a set of two error correction blocks arranged into one by the interleaving means to form one sync block, and the synchronous signal. A recording and reproducing means for recording and reproducing the sync block output from the additional circuit on a recording medium, a removing means for removing the synchronizing signal from the sync block reproduced by the recording and reproducing means, and a data output from the removing means. a deinterleaving means for dividing the error correction block into the two error correction blocks; an error correction means for performing error correction processing on the error correction block outputted from the deinterleaving means based on the error check code; 1. A digital recording/reproducing apparatus, comprising: converting means for converting an error correction block into an original input data string. (2) The recording/reproducing means records data to be recorded in NRZ.
2. The digital recording and reproducing apparatus according to claim 1, further comprising modulating means for performing I modulation and demodulating means for demodulating the reproduced data by NRZI.