JPH04183116A - Synchronous counter - Google Patents

Abstract

PURPOSE:To distribute delay time of a combined circuit to speed up the operating frequency by providing the counter with a second flip-flop for delaying the result of a first combined circuit in synchronous with the operating frequency of clock. CONSTITUTION:The first combined circuit is constituted such that a carry to FF5D occurs when FF5D is in a state one clock preceding a state that a counter carry occurs, that is, the carry occurs when FF5A is at 'L', FF5B is at 'H', and FF5C is at 'H'. Carry to FF5D that is the output from the first combined circuit is delayed by one clock by FF3 so that the counter acts normally. Further, the carry to FF5D that is delayed by one clock is compared with the present state of FF5D input to the EX-OR4C that is a second combined circuit to prepare the next state for FF5D. By the next clock edge, the next state is read in FF5D to act as the counter.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous counter that distributes the delay time of a combinational circuit and increases the operating frequency.

[Prior Art] Next, the configuration of a synchronous counter according to the prior art will be explained with reference to FIG. Figure 3 is an example of a 4-bit up counter, where IB and IC are AND gates, 2 is an inverter, 4
A to 4C are exclusive OR circuits (hereinafter referred to as EX-OR), 5A to 5D are flip-flops (hereinafter referred to as FF), 6 is a clock input terminal, and 7A to 7D are counter output terminals. Least significant bit output to 7A, terminal 7
The most significant bit output appears at D.

In Figure 3, in order to count up, FF5A~5
When all the lower bits of D become rHJ, a carry occurs, and FFs 5A to 5D are inverted by the carry.

FIG. 3 is composed of FFs 5A to 5D and a combination circuit. FF5A to 5D memorize the previous state.

The combinational circuit is composed of AND gate IB/IC, inverter 2, and Ex-oR4A to 4C, and prepares the next state from the previous state.

FF5A to 5D operate with the same clock. FF5A~
The next state of 5D is determined by the combinational circuit from the current state of FF5A to 5D, and FF5A is synchronized with the next clock.
- Stored in 5D.

The carry to FF5D is the AND of the outputs of FF5A, 5B, and 5C, and passes through AND gates IB and IC.

Furthermore, it passes through EX-OR4C, which is compared with the current state of FF5.D, and passes through three gates in total.

Next, the time chart of FIG. 3 will be explained with reference to FIG. 4. In FIG. 4, 22 is the input clock, 11 is the output of FF5A, 13 is the output of AND gate IB, 15 is the output of AND gate IC, and 16 is the EX-OR4C (7) as power. Also, T5A is FF5A (7) delay time, TlB is A
The delay time of ND gate IB, Tlo is the delay time of AND gate I
The delay time of C, T,. is the delay time of EX-OR4C.

The output 11 of FF5A, which is delayed by the delay time T5A from the edge T11 of the clock input to FF5A, is AND.
It passes through gates IB and IC and is delayed by time T1B+T1c. Furthermore, it passes through EX-OR4C, reaches the input terminal of FF5D with a delay of time T4o, and is read into FF5D at edge T12 of the next clock. At this time,
The time TB from when data 16 to FF5D is determined until it enters FF5D at clock edge T12 is
The setup time of 5D must be T5D8 or more.

Also, the time T from when the clock edge T1□ is input until the end of data 16 to FF5D. must satisfy the hold time T5DH of FF5D.

In this way, the operating frequency of the synchronous counter is FF5A
delay time and delay time of combinational circuit TA = TSA
+TIB+T,. It is determined by T4c, set-up time T5D3, hold time T, and DH of the next stage FF5D.

Next, a time chart when the operating frequency is increased by the counter shown in FIG. 3 will be explained with reference to FIG.

Reference numeral 21 in FIG. 5 is an input clock, and the rest is the same as in FIG. 4. In Figures 4 and 5, the delay time TA remains the same, so as the frequency increases and the clock period shortens, the time from when data 16 to FF5D is determined until clock edge T, 2 enters FF5D When TD becomes shorter and the time TD becomes shorter than the setup time T5DS of FF5D, the counter malfunctions.

[Problem to be Solved by the Invention] FIG. 3 shows a combination circuit that generates a carry from the lower bit, and a second combination circuit that compares the current state of FFs 5A to 5D and the carry and inverts FFs 5A to 5D. It is configured. When the number of bits in a counter is increased, the scale of the combinational circuit that generates a carry from the lower bits becomes larger and passes through many gates, which increases delay time and lowers the operating frequency.

The object of the present invention is to provide a synchronous counter that disperses the delay time of the combinational circuit shown in FIG. 3 and increases the operating frequency.

[Means for Solving the Problem] In order to achieve this object, the present invention provides a first combinational circuit that prepares a state two or more clocks ahead of the state of a first plurality of flip-flops; It includes a second flip-flop that delays the result of the circuit in synchronization with a clock, and a second combinational circuit that prepares a state one clock ahead from the output of the second flip-flop.

[Operation] Next, the structure of the synchronous counter according to the present invention will be explained with reference to FIG. FIG. 1 shows an example of a 4-bit up counter, in which IA is an AND gate, 3 is an FF, and the others are the same as in FIG. 3.

That is, FIG. 1 is ANI) gate IA and FF in FIG. 3.
3 is added, and is a combinational circuit that prepares the next state of FF5D. - The carry to FF5D is the state one clock before the state in which the carry of the counter in Fig. 3 occurs, that is, the state of the FF5D.
5A is rLJ, FF5B is rH, 1, FF5C is rHJ
The first combinational circuit is configured so that when . The first combinational circuit is constituted by an AND gate IA and an AND gate IC, which is a logical product of the inverted output of FF5A, the output of FF5B, and the output of FF5C. The carry to F'F5D, which is the output of the first combinational circuit, is
FF3 for one clock so that the counter operates normally.
delay it. The carry to FF5D delayed by one clock is input to EX-OR4C, which is a second combinational circuit, and is compared with the current state of FF5D to prepare the next state of FF5D. By being read into FF5D at the edge of the next clock, the circuit shown in FIG. 1 operates as a counter.

Next, the time chart of FIG. 1 will be explained with reference to FIG. 2. 12 in Figure 2 is the output of AND gate IA, 14 is FF
3 output, TlA is the delay time of AND gate IA, T3
is the delay time of FF3, and the other details are the same as in FIG.

Data 11, which is output after a delay time T5A from edge T11 of the clock input to FF5A, is ANDed.
The signal reaches FF3 with a delay of time T1A+T1B due to gate 1'A-IC. At this time, data 1 to FF3
The time T6 from when 3 is determined to edge T and 2 is FF
Satisfy the set-up time of 3. Then, the data 14 read into FF3 by the next edge T1□ and output with a delay of TB of FF3 reaches FF5D with a delay of time T4o by EX-OR4C. The time TF from when data 16 is determined to edge T13 at this time satisfies the setup time of FF5D.

In this way, the 4-bit up counter FF5A~
The gates between the 5Ds are divided, and the delay time of the combinational circuit, which is one of the factors that determines the operating frequency, is divided, thereby increasing the operating frequency.

[Effects of the invention] For example, when a 4-pin up counter is configured using an ECL level logic circuit, the FF delay time is 3 ns,
The delay time of the AND gate is 2.5ns, and the delay time of the EX-OR is 2.5ns. The FF setup time is about 2.5ns, and the hold time is about 1.5ns.

The highest operating frequency fmax in FIG. 3 is determined by the delay time between FF5A and FF5D, which have the largest number of gates between FFs, and the highest operating frequency fmax is as follows.

fmax= (IXIO”)/ (3+2.5X2+2
．． 5+2. 5+1. 5) = 69MHz, then the first
The maximum operating frequency of the circuit in the figure is determined between FF5A and FF3 or between FF5A and FF5C, and the maximum operating frequency f
m a x is as follows.

fmax= (IXIO”)/ (3+2.5+2.5
+2.5+1.5)=83MHz Thus, according to FIG. 1, since the FF3 is added to the combinational circuit, the delay time is dispersed, and the speed is increased by about 14 MHz compared to that in FIG. 3. Note that even if the number of bits in the counter increases, the operating frequency will not decrease if the delay time is distributed accordingly.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a synchronous counter according to the present invention;
The figure shows the time chart of Fig. 1, Fig. 3 is a configuration diagram of a synchronous counter according to the prior art, Fig. 4 shows the time chart of Fig. 3, and Fig. 5 shows the case when the clock of Fig. 3 is sped up. In the time chart, 1A~IC...AND gate, 2...group/inverter, 3...FF (flip flop), 4A~4C...EX-OR(
exclusive OR circuit), 58-5B...FF, 6
...Clock input terminal, 7A to 7D...
・Counter 8 power. Agent Patent Attorney Kin Tsukasa Komata Figure 1

Claims (1)

[Claims] 1. A first combinational circuit that prepares a state two or more clocks ahead of the state of the first plurality of flip-flops, and a second combinational circuit that delays the result of the first combinational circuit in synchronization with the clock. A synchronous counter comprising: a flip-flop; and a second combinational circuit that prepares a state one clock ahead from the output of the second flip-flop.