JPH04183146A - Communication controller - Google Patents

Abstract

PURPOSE:To shorten a period of time from time of outputting a circuit address to time when a processing request signal is returned as an interrupt by temporarily storing states of interrupt signal lines from a plurality of circuits installed in a circuit adapter at a time and detecting the presence or absence of interrupt for a plurality of circuits at a time to control a scan counter. CONSTITUTION:From scan counter 5, a circuit adapter 1001 or 1002 is selected using a circuit adapter selecting signal 101, and a state of request for processing from URT circuits 11-14 or 21-24 is output to interrupt signal lines 201-204 and stored in an interrupt register circuit 2. Here, an interrupt detecting circuit 3 monitors an interrupt state stored in the interrupt register circuit 2, and if an interrupt occurs, the interrupt detecting circuit 3 reports a circuit address of the scan counter 5 to the interrupt selecting circuit 1, and gives an internal state of the interrupt register to a processor section 6, while a circuit address output circuit 4 provides the processor section 6 with the circuit address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication control device, and particularly to a communication control device that selects and processes interrupts from a plurality of line adapters.

[Conventional technology]

Conventionally, this type of communication control device has used interrupts to detect whether there is a processing request by giving addresses to each line according to a predetermined priority order.

[Problem to be solved by the invention]

The conventional communication control device described above counts up a scan counter at a certain time, gives a line address to each line, and detects individual processing requests from the line by interrupt. Since a line processing request is detected by giving an address, extra line processing time is required, which has the drawback of reducing line processing capacity.

[Means to solve the problem]

The communication control device of the present invention includes means for generating addresses of a plurality of line adapters in a fixed order and providing them to the line adapters, means for outputting the status of a plurality of line processing requests, and a means for temporarily controlling the plurality of line interrupts of the line adapters. a register for storing interrupts in the register, a means for selecting an interrupt from the temporarily storing register, a means for detecting the presence or absence of an interrupt, and a means for providing a line address; The feature is that the presence or absence of an interrupt is detected for multiple lines at the same time.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Line adapters 1001 and 1002 are communication control devices each accommodating a line. General-purpose receiver/transmitter (URT circuit) 11 to 14. 21 to 24 are circuits that perform serial/parallel conversion of transmission/reception data, CRC calculation, synchronization control, etc.

The interrupt switching circuits 61 and 62 are connected to the line adapter 1001.
．． This is a circuit for switching interrupts 1002, and the line corresponding to the value of the line adapter selection signal line 101 is selected.

The interrupt selection circuit 1 is a circuit that outputs interrupts to the processor section 6.

The interrupt register circuit 2 is connected to the line adapter 1001.
1002 interrupts are simultaneously input and output to the processor section 6.

The interrupt detection circuit 3 monitors the interrupt state and instructs the scan counter to count up if there is no interrupt.

The line address output circuit 4 is a circuit that outputs an interrupt address to the processor.

The scan counter 5 is updated by +1 and outputs the output to the line adapter selection signal line 101.

The line adapter selection signal line 101 is connected to the line adapter 100
This is a signal line for identifying 1.1002.

The line address selection signal line 102 is connected to the line adapter 100.
This is a signal line for identifying the URT circuits 11 to 24 of 1.1002.

The interrupt output signal line 103 is a signal line for outputting the interrupt selected by the interrupt selection circuit 1.

The address signal line 104 is a signal line for causing the processor unit 6 to identify the URT circuits 11 to 24.

The interrupt signal lines 201 to 204 are connected to the line adapter 100.
1.1002 interrupt signal line.

The operation shown in FIG. 1 will be explained. First, the line adapter 1001 or 1002 is selected from the scan counter 5 using the line adapter selection signal line 101. The selected line adapter 1001 or 1002 outputs the status of the processing request from the URT circuits 11 to 14 or 21 to 24 housed therein to the interrupt signal lines 201 to 204, and stores it in the interrupt register circuit 2.

The interrupt detection circuit 3 monitors the interrupt state stored in the interrupt register circuit 2, and if there is no interrupt, counts up the scan counter 5 to detect the next multiple line interrupt of the line adapter. If there is an interrupt, the line address of the scan counter 5 is reported to the interrupt selection circuit 1, the state in the interrupt register is given as an interrupt to the processor section 6, and at the same time, the line address output circuit 4 sends the line address to the processor section 8. Give address.

〔Effect of the invention〕

As explained above, the communication control device of the present invention temporarily stores the states of interrupt signal lines from multiple lines housed in a line adapter in an interrupt register, and detects the presence or absence of an interrupt for multiple lines at once. Since the scan counter is controlled, the time required for the processing request signal to be returned as an interrupt after the line address is output is shortened, which has the effect of increasing line processing efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention. 1001-1002...Line adapter, 11-24.
... URT circuit, 101... Line adapter selection signal line, 102... Line address selection signal line, 103...
Interrupt output signal line, 104...Address signal line, 2
01-204...Interrupt signal line, 1...Interrupt selection circuit, 2...Interrupt register circuit, 3...Interrupt presence detection circuit, 4...Line address output circuit,
5...Scan counter, 6...Processor section.

Claims (1)

[Claims] means for generating addresses of multiple line adapters in a fixed order and providing them to the line adapter; means for outputting the status of multiple line processing requests; a register for temporarily storing multiple line interrupts of the line adapter; means for selecting an interrupt from a register stored in the register, means for detecting the presence or absence of an interrupt, and means for providing a line address;
A communication control device characterized in that interrupts from a plurality of lines are simultaneously stored in the register, and the presence or absence of an interrupt is detected for the plurality of lines at once.