JPH0418334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital adder circuit having a rounding operation function.

[Technical background of the invention and its problems]

In digital calculations, for example, it is necessary to perform calculations such as in a transversal filter that sequentially adds the product of an input signal and a weighting coefficient, rounds the addition result to a certain word length, and outputs the result.

FIG. 1 shows the basic configuration of an adding circuit having an arithmetic function of sequentially adding the products of the above-mentioned input signals and weighting coefficients. This addition circuit is composed of half adders 11 and 12, an OR circuit 13, and a one-clock delay element 14. Half adders 11 and 12 output the exclusive OR and AND of these inputs when two inputs are added to the input terminals X ₁₁ , Y ₁₁ , X ₁₂ , and Y ₁₂ .
It has a logic function to output from U ₁₁ , V ₁₁ , U ₁₂ , V ₁₂ , and when the inputs of these half adders 11 and 12 are X and Y, and the outputs are U and V, the input X,
The relationship between Y and the outputs U and V can be expressed as U=XY V=X・Y (1). Here, the disjunction and .are logical operation symbols that mean logical product.

In the circuit shown in FIG. 1, when input signals A and B are input to the input terminals X ₁₁ and Y ₁₁ of the half adder 11,
The output signal AB is output from the output terminal U ₁₁ , and the output signals A and B are output from the output terminal V ₁₁ . The signals output from the output terminal V _{11 of the half adder 11} and the output terminal V ₁₂ of the half adder 12 are connected to the OR circuit 1.
If the output signal obtained by calculation in step 3 is Cn, then
The output signal Cn is delayed by one clock by the delay element 14 and fed back to the input terminal X12 of the half adder ₁₂ as a carry signal Cn _-1 .

Then, the output signals A and B from the output terminal V ₁₁ of the half adder 11 and the output signals A and Cn _-1 B and Cn _-1 from the output terminal ₁₂ of the half adder 12 are input to the OR circuit 13. , an output signal of Cn=A.B+A.Cn _-1 +B.Cn _-1 (2) is output from the output terminal of the OR circuit 13. Here, + is a logical operation symbol meaning a logical sum. The output of this adder circuit is output from the output terminal _U12 of the half adder 12 as an output signal of S'. Output signal S′ is a carry signal
It is a negative logical sum of Cn _-1 and the output signal AB of the output terminal U ₁₁ , and can be described by S'=ABCn _-1 . . . (3).

Next, the basic configuration of a rounding circuit that rounds the result of successive addition to a certain word length and outputs the result will be explained with reference to FIG. This rounding circuit includes a half adder 21, an AND circuit 2
It is composed of 2, 23 delay elements 24, 25, and an OR circuit 26. Input terminal of half adder 21
A gate signal is applied to X ₂₁ in the AND circuit 22.
The input signal of the rounding circuit with a word length of P bits is determined by GR _A.
Signal with the lower (P-q) bits of S' masked
S ₁ ′ is input. Input terminal Y ₂₁ has AND circuit 2
3, the gate signal GR _B causes the input signal to
The signal S ₂ ' with the lower (P-q-1) bits and upper q bits of S ₁ ' masked and the carry output signal Cn of the output terminal V ₂₁ of the half adder 21 are transmitted through delay elements 24 and 25, respectively. The carry signal Cn _-1 calculated by the OR circuit 26 is input. As a result, the output signal S of the rounding circuit is outputted from the output terminal U ₂₁ of the half adder 21, and can be expressed as S=S ₁ 'Cn _-1 . Output signal S is input signal
This is a signal with a word length of q bits in which the (P-q)th bit of S' is rounded down to zero. Here, the carry output signal Cn can be expressed as Cn=S ₁ '·Cn _-1 .

In this way, adder circuits and rounding circuits are generally configured separately, so when an LSI includes a large number of adder circuits and rounding circuits, it is important to avoid this from affecting the overall configuration and complicating it. I can't.

As mentioned above, the addition circuit and the rounding circuit are basically constructed of half adders, so if two operations are not performed at the same time, the half adder is shared and the addition and rounding operations are performed. is possible.

[Purpose of the invention]

This invention was made in view of the above circumstances, and aims to provide a digital adder circuit that is capable of performing two operations, addition and rounding, and whose overall configuration can be simplified even when a large number of digital adders are used. .

[Summary of the invention]

The present invention includes a digital addition circuit including first and second half adders, first and second AND circuits,
It is composed of an OR circuit and a delay element, and these components including a half adder are shared for addition operations and rounding operations.

That is, the present invention provides a digital adder circuit having an addition mode and a rounding operation mode for rounding the word length P of the addition output signal S' in the addition mode to a predetermined word length q where q<P. a first half adder 31 which receives an input signal A which is always given a low level in the rounding operation mode and the addition output signal S' and generates an exclusive OR output and an AND output; It receives the exclusive OR output from the first half adder 31 and the carry input signal Cn _-1 to generate an exclusive OR output and an AND output, and uses the addition output signal S' as the exclusive OR output in the addition mode. The second half adder 32 and the addition output signal S' are always at a low level in the addition mode, and in the rounding operation mode, the addition output signal S' is (P-q+
1) A first AND circuit 34 that receives as input the first gate signal G _A that is at a high level at the p-th bit and becomes a low level during other periods, and the output of this first AND circuit 34. the first and second half adders 3;
an OR circuit 35 which generates a carry output signal Cn by inputting AND outputs from the OR circuits 1 and 32; and a delay element 3 which delays the carry output signal from the OR circuit 34 to obtain the carry input signal Cn _-1 .
6, the addition output signal S', and a second signal which becomes a high level at the (P-q)th bit of the addition output signal S' and a low level during other periods in the rounding operation mode.
The rounded output signal S is input with the gate signal GR _B of
It is characterized by comprising a second AND circuit 33 that generates .

〔Effect of the invention〕

According to this invention, two operations, addition and rounding, can be performed in one
It can be realized with a relatively simple configuration of
This is advantageous when a large number of such circuits are required, such as in an LSI, and the overall simplification and cost reduction can be achieved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 3 shows a case where the present invention is applied to an accumulation/addition circuit. The first as shown in the figure
and a second half adder 31, 32, a two-input first
It is composed of second AND circuits 33 and 34, a three-input OR circuit 35, a one-clock delay element 36, and a memory 37. The input signal A and the output signal B of the memory 37 are sent to the first half adder 31
is input to input terminals X ₃₁ and Y ₃₁ of. The exclusive OR output is input from the output terminal U ₃₁ to the input terminal Y 32 of the half adder 32, and the AND output is input from the output terminal U 31 to the input terminal Y ₃₂ of the half adder 32.
V ₃₁ is input to the input terminal 35b of the OR circuit 35.

On the other hand, the input terminals 34a and 34 of the AND circuit 34
The input signal B and the second gate signal GR _B are input to the input signal B, and the output signal B ₂ ' is input to the input terminal 35c of the OR circuit 35. A carry output signal Cn is outputted from the OR circuit 35, delayed by one clock in a delay element 36, and fed back to the input terminal X32 of the second half adder ₃₂ as a carry input signal Cn _-1 . Output signal from output terminal U ₃₂ of half adder 32
S' is input to the memory 37, and its output signal is input to the input terminal 33a of the AND circuit 33. At this time, the first gate signal G _A is input to the input terminal 33b of the AND circuit 33, and the output signal S is output from the AND circuit 33. The output signal of the output terminal V ₃₂ of the half adder 32 is input to the input terminal 3 of the OR circuit 35.
5a.

In addition operation, for example, when input signal A is added sequentially to N circuits, the gate signal GR _B becomes "L", so the portion surrounded by the broken line in the figure is the same as the operation in FIG. 1. Therefore, the addition output signal S' and the carry output signal Cn can be described by the equation (2) Cn=A・B+A・Cn _-1 +B・Cn _-1 ……(2) in the same way as above. can. The output of this circuit is output from the output terminal U 32 of the half adder ₃₂ as an output signal S'. Output signal S′ is a carry signal
As the exclusive OR of Cn _-1 and the output signal AB of the output terminal U ₃₁ of the half adder 31, the formula (3) is used as described above.
It can be described by S'=ABCn _-1 (3). In this way, the addition operation can be performed.

On the other hand, in a rounding operation, for example, when rounding the successive addition result S' of word length P bits to S of word length q bits, input signal A becomes "L", and gate signal G _A becomes (P
-q+1) ~ “H” at Pth bit, “L” at other bits
Further, the gate signal GR _B becomes "H" at the (P-q)th bit and "L" at the other bits. At this time,
Lower 1 to (P-q-1) of signal B with word length P bits
The bit part is B ₃ ', and the (P-q) bit part is
B ₂ ', upper (P-q+1) to P bit part
Assuming B ₁ ′, the output of the rounding circuit is as follows.

() When 1≦n<P−q, the output of the AND circuit 34 is “L”, and the output of the output terminal V ₃₂ of the half adder 32, V=B ₃ ′・Cn ₋₁ , is also “L” (C ₀ is “L”), so the rounded output signal S′ is the input signal
B ₃ ′ is output as is.

() When n=P-q, the output of the AND circuit 34 is B ₂ ', and the carry input signal Cn _-1 is "L" since the carry output signal Cn one bit earlier is "L", so the rounded output signal S' is It is equal to the input signal B ₂ ′, and the carry output signal Cn is also equal to B ₂ ′.

() When P-q<n≦P, the rounded output signal S' becomes equal to the input signal B 1 ' if the input signal B ₂ ' one bit before is "L", and the input signal B _{2 '} is "H"
If so, the signal becomes a signal in which "1" is added to the LSB of the input signal B ₁ '. The lower (P-q) bit parts (B ₃ ' and B ₂ ') of the rounded signal S' are masked by the gate signal GR _A , and the upper q bit parts B ₁ ' become the rounded output signal S. is output as

Therefore, with this configuration, if two operations are not performed simultaneously, it is possible to add a rounding operation function to the addition circuit by sharing the half adder etc. that constitute the addition circuit. , the configuration can be simplified and the cost can be reduced.

FIG. 4 shows a configuration that further embodies the above-mentioned embodiment, including 3-input AND circuits 41 to 44, 4-input AND circuits 45 and 50, 2-input AND circuits 46 to 49, and 2-input AND circuits 41 to 44. It is constructed of an AND circuit 51, a one-clock delay element 52, and NOT circuits 53-55. The AND circuit 41 receives the input signals A, _B and the carry signal Cn _-1 ; Output signal, input signal B and inversion circuit 5
3, _and the output signal of the NOT circuit 54, the output signal of the NOT circuit 55, and the carry signal Cn _-1 are input to 44. The output signals of these AND circuits 41 to 44 are input to one input terminal of a two-input AND circuit 51. The gate signal G _A is input to the other input terminal of the AND circuit 51, and the output signal S is output from the output terminal.

On the other hand, the input signals A and B are input to the AND circuit 46.
47 has input signal A, carry signal Cn _-1 , 4
8 has input signal B, carry signal Cn _-1 , 49
input signal B, gate signal GR _B , gate signal
GR _B is input. These AND circuits 46 to 4
9 is input to the input AND circuit 50, and its output signal is delayed by one clock by the delay element 52 to become the carry input signal Cn _-1 , and as described above, the output signal is input to the AND circuit 50, and the output signal is delayed by one clock by the delay element 52 to become the carry input signal Cn-1. is input. On the other hand, the carry input signal Cn _-1 is supplied to the inverter 53
is inverted and input to AND circuits 42 and 43.

With the above configuration, this adder circuit can perform addition operations and rounding operations in the same manner as in FIG. 3.

Next, FIG. 5 shows another configuration that further embodies the embodiment shown in FIG. 3, in which a two-input AND circuit 61
~63, 66~68, 3-input negative AND circuit 6
4, 4-input negative OR circuit 65, 3-input negative OR circuit 70, 2-input negative AND circuit 69, 71,
73, and a one-clock delay element 72.

One input terminal of each of the AND circuits 61 to 63 receives input signals A, B, and a carry input signal.
Cn _-1 is input, and the output signal Cn' of the OR circuit 70 is commonly input to the other input terminal. The input terminals of the AND circuit 64 receive the input signals A, B and the carry input signal Cn _-1 , and the input terminals 66 receive the input signals A, B and the carry input signal Cn -1.
B, 67 has input signal A, carry signal Cn _-1
However, input signal B and carry signal Cn _-1 are input to 68. The gate signal GR _B and the input signal B are input to the input terminal of the negative OR circuit 69 . In addition, the input terminals of the negative OR circuit 65 are connected to the AND circuits 61 to 61.
64 output signals are input. The output signal of the negative OR circuit 65 and the gate signal G _A are input to the negative AND circuit 73, and the output thereof becomes the output signal S.

An AND circuit 6 is connected to the input terminal of the negative logic divider circuit 70.
6 to 68 output signals are input. The output signal of the negative OR circuit 70, the negative AND circuit 69, and the output signal are input to the negative AND circuit 71, and the output thereof is delayed by one clock by the delay element 72 and becomes the carry input signal Cn _-1 . .

With the above configuration, the adder circuit can perform addition operations and rounding operations in the same manner as in the case of FIG.

Note that this invention is not limited to the above embodiments. Various modifications can be made without changing the gist.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the basic configuration of a conventional adding circuit, FIG. 2 is a circuit diagram showing the basic configuration of a conventional rounding circuit, and FIG. 3 is a circuit diagram showing an embodiment of the present invention. , FIG. 4 or FIG. 5 are circuit diagrams showing a more specific configuration of this embodiment. 11, 12... Half adder, 13... OR gate, 14... 1 clock delay element, X ₁₁ , Y ₁₁ ,
X ₁₂ , Y ₁₂ ... Input terminal, U ₁₁ , V ₁₁ , U ₁₂ , V ₁₂ ...
...Output terminal, A, B...Input signal, Cn, S'...
Output signal, Cn _-1 ... Carry signal, S ₁ '... Input signal, 21... Half adder, 22, 23... AND circuit, 24, 25... Delay element, 26... OR circuit, GR _A , GR _B ...Gate signal, _X21 , _Y21 ...
...Input terminal, U ₂₁ , V ₂₁ ... Output terminal, S ... Output signal, 31, 32 ... Half adder, 33, 34 ...
...2-input AND gate, 35...3-input OR circuit, 33a, 33b, 34a, 34b, 35
a to 35c...Input terminal, 36...1 clock delay element, 37...Memory, X ₃₁ , Y ₃₁ , X ₃₂ ,
Y ₃₂ ... Input terminal, U ₃₁ , V ₃₁ , U ₃₂ , V ₃₂ ... Output terminal, 44' to 44 ... 3-input AND circuit, 4
5, 50... 4-input OR circuit, 46 to 49,
51...2-input AND circuit, 52...1-clock delay element, 53-55...NOT circuit, Cn _-1 ,
A,... Output signal, 61-63, 66-68...
...2-input AND circuit, 64...3-input AND circuit, 65...4-input negative AND circuit, 69,7
1, 73...2-input negative AND circuit, 70...3
Input negative OR circuit, 72...1 clock delay element.

Claims (1)

[Scope of Claims] 1. A digital adder circuit having an addition mode in which input signals are sequentially added and a rounding operation mode in which the word length P of the addition output signal in the addition mode is rounded to a predetermined word length q such that q<P, a first half adder which receives an input signal to which an augend input is applied in an addition mode and is always given a low level in a rounding operation mode, and the addition output signal, and generates an exclusive OR output and an AND output; , a second half adder which receives the exclusive OR output and the carry input signal from the first half adder, generates an exclusive OR output and an AND output, and obtains the addition output signal as an exclusive OR output in the addition mode. a half adder, and the addition output signal is always at a low level in the addition mode, and in the rounding operation mode, the (P-q+1) to Pth bits of the addition output signal are at a high level, and the addition output signal is at a low level during other periods. a first AND circuit which receives a gate signal of 1 as an input, and generates a carry output signal by inputting the output of the first AND circuit and the AND outputs from the first and second half adders. a delay element that delays a carry output signal from the OR circuit to obtain the carry input signal; and a (P-q) bit of the addition output signal in the rounding operation mode. A second gate signal which generates a rounded output signal by inputting a second gate signal which is at a high level during the first period and a low level during other periods.
What is claimed is: 1. A digital adder circuit comprising: an AND circuit;