JPH0418338B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity generation method for generating correct data parity bits in parallel with correction of a 1-bit error in a read data portion in a storage device using an IC memory.

Conventionally, this type of storage device has the configuration shown in FIG. 1, in which a check bit generator 1,
It comprises a memory 2, a syndrome generator 3, a decoder 4, a 1-bit error corrector 5, and a read data parity generator 12. Write data 6 and the output of the check bit generator 1 are input to the write side of the memory 2. On the other hand, on the read side, syndrome generator 3
Read data (before correction) 9 and check bits 8 outputted from the memory 2 are inputted, and syndrome bits 10 outputted from the generator 3 are inputted to the decoder 4. And 1
The read data (before correction) 9 and the output of the decoder 4 are input to the bit error corrector 5, and the corrector 5 outputs read data (after correction) 11.

Conventionally, in this type of storage device, when a 1-bit error is detected in the read data section, in order to correct the error bit and generate a correct parity bit, the syndrome generator 3, decoder 4, and 1-bit error correction are required to correct the error bit and generate a correct parity bit. This is done by inputting the corrected read data 11 through the parity generator 12 through the parity generator 12. Therefore, the conventional parity generation method has a drawback that the output of read data parity bits is slower than that of data bits.

The present invention was made in view of these drawbacks,
By generating read data parity by calculating the exclusive OR of check bits and syndrome bits, the above drawbacks are solved, the amount of hardware is reduced,
Furthermore, the present invention provides a parity generation method that outputs the parity with a short delay time.

That is, the present invention generates a syndrome bit from read data and a check bit, inputs this syndrome bit to a decoder to detect the position of a 1-bit error, and corrects the bit error in the read data using a 1-bit error corrector. In the parity generation method in a memory device configured to a read data parity generator that generates
and a read data parity corrector for inverting the parity bit output from the read data parity generator when a 1-bit error is detected in the read data part.
When a bit error is detected, correct data parity bits are generated in parallel with correction of the error bit.

Hereinafter, the present invention will be explained based on embodiments shown in the drawings.

FIG. 2 is a block diagram showing a storage device to which an embodiment of the parity generation method of the present invention is applied.

In the figure, the storage device equipped with the parity generation method of the present invention is composed of a check bit generator 1, a memory 2, a syndrome generator 3, a decoder 4, and a 1-bit error corrector 5.
Furthermore, a read data parity generator 12;
It is comprised of a data 1-bit error detector 13 and a read data parity corrector 14.

On the write side of the memory 2, write data 6 and
The output of check bit generator 1 is input. That is, during writing, a check bit is added to the write data 6 sent from a central control unit (not shown) by the check bit generator 1, and
Written to memory 2. In this case, the write data parity is used only for checking and is not written to memory 2.

On the other hand, read data (before correction) 9 and check bits 8 are output from the read side of the memory 2.
The former is input to the 1-bit error corrector 5 and the syndrome generator 3, and the latter is input to the syndrome generator 3 and the read data parity generator 12. Syndrome bit 10 output from this syndrome generator 3
is input to each of the decoder 4, read data parity generator 12, and data 1-bit error detector 13. The output of the decoder 4 is input to the 1-bit error corrector 5, which corrects the read data 9, and causes the corrector 5 to output the read data (after correction) 11. Further, each output of the read data parity generator 12 and the data 1-bit error detector 13 is connected to the read data parity corrector 1.
4 and causes read data parity 7 to be output.

Figure 3 shows data length 16 applied to the above invention.
FIG. 3 is an explanatory diagram showing an example of a Hamming coat in the case of bits. In the example shown in the figure, a total of 22 bits, including 16 data bits and 6 check bits, are written into the memory 2.

Here, check bit C0 is data 0, 1,
Parity of 2nd, 3rd, 4th, 5th, 10th, 14th bit,
C1 is the parity of data 0, 1, 2, 6, 7, 8, 9th bit, C2 is data 0, 4, 6, 7, 8,
Parity of 13th, 14th, 15th bit, C3 is 5, 6,
Parity of 9th, 10th, 11th, 13th, 14th, 15th bit,
C4 is parity of 1st, 3rd, 7th, 9th, 10th, 11th, 12th, 13th bit, C5 is data 2nd, 3rd, 4th, 5th, 8th,
It has parity on the 11th, 12th, and 15th bits.

When reading, the read data 9 and check bit 8 are input to the syndrome generator 3 to generate syndrome bit 10, and this syndrome bit 10 is input to the decoder 4 to determine the location of a 1-bit error or whether it is a 2-bit error. is being detected. In the present invention, the parity of the read data is generated by checking the parity of all syndrome bits 10 and all check bits 8 at the same time as this detection operation.

FIG. 4 is a block diagram showing details of an example of the parity generation method of the present invention using the Hamming coat. In the syndrome bit 10 output from the syndrome generator 3 shown in the figure,
10a is data 0, 1, 2, 3, 4, 5, 10, 14
The parity of the 1st bit and C0 bit, 10b is the parity of data 0, 1, 2, 6, 7, 8, 9th bit and C1, 10c is the data 0, 4, 6, 7, 8,
13th, 14th, 15th bits and parity of C2, 10d is data 5th, 6th, 9th, 10th, 11th, 13th, 14th, 15th bit and parity of C3, 10e is data 1st, 3rd, 7th,
Parity of 9th, 10th, 11th, 12th, 13th bit and C4,
10f is data 2, 3, 4, 5, 8, 11, 12, 15
It is the parity of bit and C5.

If we take the parity of the syndrome bits 10a to 10f and all check bits, the influence of the check bits disappears on these parity bits.
The desired read data parity for data bits 0 to 15 is determined. Here, if there is a 1-bit error in the data portion, it is detected by the 1-bit error detector 13 and the parity bit is inverted.

Note that even when the data is 32 bits, 64 bits, etc., read data parity can be generated using the same method.

As described above, the present invention generates read data parity using check bit syndrome and bits in parallel with one-bit correction of data, and therefore has the effect of outputting the parity with a short delay time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional parity generation method, FIG. 2 is a block diagram showing an embodiment of the parity generation method of the present invention, and FIG. 3 is a case of 16-bit data length applied to the present invention. FIG. 4 is a block diagram showing details of an example of the parity generation method of the present invention using the Hamming code. 1...Check bit generator, 2...Memory, 3...Syndrome generator, 4...
Decoder, 5... 1-bit error corrector, 6... Write data, 7... Read data parity, 8... Check bit, 9... Read data (before correction), 1
0... Syndrome bit, 11... Read data (after correction), 12... Read data parity generator, 13... Data 1-bit error detector, 14
...Read data parity corrector.

Claims (1)

[Claims] 1 A syndrome bit is generated from read data and a check bit, the syndrome bit is input to a decoder to detect the position of a 1-bit error, and a 1-bit error corrector corrects the bit error in the read data. In the parity generation method in a memory device equipped with an error correction function, the syndrome bit
a data 1-bit error detector for detecting whether or not a bit error exists in the data section; a read data parity generator for generating a parity bit for read data from the syndrome bit and check bit; and a read data parity corrector that inverts the parity bit output from the read data parity generator when an error is detected, and when a 1-bit error is detected in the read data section, the error bit is inverted. 1. A parity bit generation method for a memory device, characterized in that the method is configured to generate correct data parity bits in parallel with correction of data parity bits.