JPH0418377U

JPH0418377U -

Info

Publication number: JPH0418377U
Application number: JP5980290U
Authority: JP
Priority date: 1990-06-06
Filing date: 1990-06-06
Publication date: 1992-02-17

Description

[Brief explanation of drawings]

第１図はこの考案の実施例を示すブロツク図、
第２図はその動作を説明するためのタイムチヤー
ト、第３図は小レベル不要パルスの問題を説明す
るための波形図、第４図は従来の試験装置を示す
ブロツク図、第５図は不要パルスの例を示す図、
第６図は従来の不要パルスの検出法を示す図、第
７図はその問題点を説明するための図、第８図は
第７図の問題を解決した従来の不要パルス検出法
を示す図である。 Figure 1 is a block diagram showing an embodiment of this invention.
Figure 2 is a time chart to explain its operation, Figure 3 is a waveform diagram to explain the problem of small level unnecessary pulses, Figure 4 is a block diagram showing the conventional test equipment, Figure 5 is unnecessary. Diagram showing an example of a pulse,
Figure 6 is a diagram showing the conventional unnecessary pulse detection method, Figure 7 is a diagram to explain the problem, and Figure 8 is a diagram showing the conventional unnecessary pulse detection method that solves the problem in Figure 7. It is.

Claims

[Scope of Utility Model Registration Claim] A pattern generator that applies a test pattern to a logic device under test; a counter that counts the number of edges of an output waveform of the logic device under test; and after applying a predetermined number of test patterns, means for detecting whether the number of edges between the predetermined number of test patterns obtained from the counter matches the number of edges of the expected waveform for the predetermined number of test patterns; and a logic device testing apparatus comprising: .