JPH0418657A - Microcomputer I/O bus - Google Patents

Abstract

PURPOSE:To unnecessitate an external wait generating circuit and to reduce man-hour for design and manufacture by generating an I/O wait signal by a wait generator in a microprocessor which can control a program according to the instruction of a microcomputer. CONSTITUTION:An address is decoded by a decoder 41 and a chip A select signal is turned on. After 4 waits, an effective data is loaded from the chip A onto an I/O data bus. A subtraction counter 36 starts subtraction according to address strobe and continuously outputs the wait signal to control logic 34 until turning to 0. After 4 waits, the wait signal is turned off and the effective data on the I/O data bus is read into an R0 of a register file 37. Further, wait is loaded with the wait number 4 preserved in a count register 35 similarly according to the next LOAD (F001h)R1 instruction as well, and the data is read into the R1 register synchronously with the effective data output of a chip B. Thus, the wait signal is controlled on the inside in the manner of a software corresponding to the timing of the chip of the external I/O bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer I/O bus that connects peripheral chips having various timings in a microcomputer system.

[Prior art] Taking an example of a conventional microcomputer, the second
As shown in the figure, a microprocessor 11 outputs an address to an I/O address bus, a decoder 13 decodes it, and outputs a select signal to a peripheral chip group 14 and a wait generator 12. The weight generator 12 is the microprocessor 1
By generating an I/O wait signal for 1, data input/output on an I/O data bus between a peripheral chip and a microprocessor is delayed and bus timing is controlled.

[Problems to be Solved by the Invention] However, in the conventional method, weight control is required for each chip, and as the number of peripheral chips increases, the weight generation circuit becomes larger, increasing both design cost and manufacturing cost.

[Means for Solving the Problems] As shown in FIG. 1, in the microcomputer I/O bus of the present invention, a microprocessor 1 outputs an address to an I/O address bus, a decoder 3 decodes it, and a peripheral chip group 4 I/O between the peripheral chip and the microprocessor is synchronized with the output of the select signal by the wait generator 2 inside the microprocessor, which can be program-controlled by instructions from the microcomputer, to generate ■/○ wait signals. Delay data input/output on the O data bus.

[Example] FIG. 3 shows an example of the present invention. This is chip A and address FO connected to address FOOOh of the ■/○ bus.
This is a case where data is fetched in 4 waits from chip B connected to O1h. As a microprocessor instruction,
Assume a SET instruction that sets the wait number of the I/O bus and a LOAD instruction that loads data from a certain address into a register. The operation will be explained according to FIG.

The microcomputer 3 in FIG. 3(a) has an instruction area 3.
1 is fetched into the instruction queue 32 and decoded by the instruction decoder 33. ” SET 4wa i
In the case of the t' instruction, the wait number of 4 is controlled by the register set signal of the control logic 34, and is taken into the count register 35 and stored. In the next "LOAD (FOOOh) RO' command, the wait number stored in the count register 35 is first loaded into the subtraction counter 36 under the control of the counter set of the control logic 34. Furthermore, the address data FOOOh flows to the I/O address bus, and the address strobe is turned on. The address is decoded by the decoder 41 in FIG. 3(b), the chip hole select signal is turned ON, and after 4 waits, valid data from chip A is placed on the I/O data bus. The subtraction counter 36 starts subtraction by the address strobe and continues to output a wait signal to the control logic 34 until it reaches 0. After 4 waits, the wait signal turns OFF and the 37th register file RO
Valid data on the I/O data bus is read. Furthermore, in the next ``LOAD (Foolh) R1' instruction, a wait is applied with the wait number 4 stored in the count register 35, and the data is read into the R1 register in synchronization with the effective data output of chip B. In this way, the wait signal is controlled internally by software to match the timing of the chip on the external I/O bus.

FIG. 4 shows another embodiment of the invention. Similarly to Figure 3, I
This is a case where data is fetched in 4 waits from chip A connected to address FOOOh of the /O bus and chip B connected to address FOO1h. l0LOAD is a microprocessor instruction that loads data from a certain address into a register while setting the wait number of the I/O bus.
Assume the command. The operation will be explained according to FIG.

The microcomputer 50 fetches instructions on an instruction area 51 into an instruction queue 52 and decodes them with an instruction decoder 53. 'IOLOAD(FOOOh)4wa
With the i t RO' command, the wait number is first taken into the subtraction counter 55 at the timing when the control logic 54 sets the counter. Furthermore, the address data FOOOh flows to the I/O address bus, and the address strobe is turned on. The subtraction counter starts subtraction by the address strobe and continues to output a wait signal to the control logic 54 until it reaches 0. After 4 waits, the wait signal turns OFF and the register file 56 RO
Valid data on the I/O data bus is read. Next゛ IOLOAD(FOOOh)4wa it
The RO' instruction operates in exactly the same way.

In the embodiment shown in FIG. 3, once the wait number is initialized in the counter register, there is no need to set it again until the wait number changes, but in the embodiment shown in FIG. 4, it is set for each instruction. . When the weight number does not change much, the method shown in FIG. 3 is better, but when the weight number changes significantly, the method shown in FIG. 4 is better. The count register and subtraction counter correspond to the weight generator shown in FIG. 1.

Note that it is inefficient for the user to directly program the wait number while considering the I/O bus address, so it is not efficient for a compiler etc. to check the I/O address to be accessed and automatically create wait number data and attach it to the program. By adding this, the burden on the user's program will hardly increase.

[Effects of the Invention] As described above, according to the present invention, an I/O wait signal is generated in a microcomputer I/O path by a wait generator inside a microprocessor that can be program-controlled by microcomputer instructions. No external weight generation circuit is required, and design and manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a microcomputer I/O bus according to the present invention. FIG. 2 is a block diagram showing the configuration of a conventional microcomputer I/O bus. FIG. 3 is a detailed block diagram showing one embodiment of the microcomputer I/O bus of the present invention. FIG. 4 is a detailed block diagram showing one embodiment of the microcomputer I/O bus of the present invention.・Microprocessor, weight generator, decoder, peripheral chip group ・Microprocessor, weight generator, decoder, peripheral chip group 30 ・ ・ 31 ・ ・ 32 ・ ・ 33 ・ 34 ・ ・ 35 ・ ・ 36 ・ ・ 37 ・ ・41 ・ ・ 42 ・ ・ 43 ・ ・ 50 ・ ・ 51 ・ ・ 52 ・ ・ 53 ・ ・ 54 ・ ・ 55 ・ ・ 56 ・ ・ ・ Microprocessor・Instruction area・Instruction queue・Instruction decoder・Control logic・Count register・Subtraction Counter, register file, decoder, chip A, chip B, microprocessor, instruction area, instruction queue, instruction decoder, control logic, subtraction counter, register file

Claims (1)

[Claims] In a microcomputer system that connects peripheral chips with various bus timings and controls data input/output, the microprocessor outputs an address to the I/O address bus, the decoder decodes it, and sends a select signal to a group of peripheral chips. Data on the I/O data bus between the peripheral chip and the microprocessor is generated by generating an I/O wait signal in a wait generator inside the microprocessor that can be program-controlled by instructions from the microprocessor. A microcomputer I/O bus characterized by delaying input/output.