JPH041868B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a rotation speed detection circuit using a resolver,
In particular, the present invention relates to a circuit that detects the rotational speed of a rotating body based on a sinusoidal signal having a frequency corresponding to the rotational speed output from a resolver.

[Prior art] Many resolvers have been used as position detectors in machine tools, and among them, plasticless resolvers are widely used as position detectors in numerical control mechanisms because they are highly accurate and can rotate at high speeds. It's here. Furthermore, in recent years, resolvers have also been used as speed detectors. Now, the time
Let the rotation angle of the resolver at t ₁ be θ ₁ , and at time t ₂
If the rotation angle at is θ ₂ , then (θ ₂ −θ ₁ )/
(t ₂ /t ₁ ) is the change in rotation angle per unit time. Therefore, the rotational speed of the rotating body can be detected by measuring the change per unit time in the arbitrary rotation angle θ of the sinusoidal signal output from the resolver.

However, this means of detecting the rotational speed by directly utilizing the sinusoidal signal output from the resolver has a drawback in that highly accurate detection cannot be performed. The reason for this is that during one revolution of the resolver, there is always one point where the resolver origin, that is, the phase of the input signal and the output signal match, and the rotation angle θ is measured with this resolver origin as a reference. However, due to the characteristics of resolvers, there is discontinuity in the input/output relationship near the resolver origin, so it is not possible to accurately measure the rotation angle θ from the resolver origin.
As a result, the rotational speed can be detected with high precision.

[Problems to be Solved by the Invention] Therefore, a square wave signal P ₀ as shown in FIG. 1 is obtained based on the output of the resolver, a clock pulse Pc is obtained by a pulse generation circuit, and the square wave signal P ₀ It was considered that the rotational speed of the rotating body could be detected by measuring the pulse width T ₀ of the clock pulse Pc using the period of the clock pulse Pc as a measure.

In this case, the above-mentioned pulse width T ₀ can be measured more accurately as the period Tc of the clock pulse Pc is shortened, but the rising and falling times of the square wave signal P ₀ are the rising and falling times of the clock pulse Pc. Since it does not match the falling time,
No matter how short the period Tc of the clock pulse Pc is, fractions of the time widths ΔT ₁ and ΔT ₂ will occur near the rise and fall of the square wave signal _{p 0} , respectively. Accurate measurement is not possible, and the rotational speed cannot be detected with high precision.

[Object of the Invention] An object of the present invention is to provide a rotational speed detection circuit using a resolver that can detect the rotational speed of a rotating body with high precision using a resolver as a detection element.

[Means for Solving the Problems] In order to solve the above-mentioned problems, the first invention of the present application uses a waveform shaping circuit to generate a sinusoidal signal having a frequency corresponding to the rotational speed output from the resolver. A resolver converts the signal into a square wave signal, measures the pulse width of the square wave signal using a clock pulse output from a clock pulse generation circuit, and outputs a voltage signal corresponding to the rotational speed of the rotating body based on the measured value. In the rotational speed output circuit used, a first fractional pulse having a pulse width that receives the square wave signal and the clock pulse, rises at the rising edge of the square wave signal, and falls at the rising edge of the first clock pulse input thereafter; a fractional pulse generating circuit that generates a second fractional pulse having a pulse width that rises at the falling edge of the square wave signal and falls at the rising edge of the first clock pulse input thereafter; a pulse width expansion circuit that receives the first and second widened fractional pulses and outputs first and second widened fractional pulses by expanding the pulse width of each fractional pulse by a predetermined multiple; A subtraction circuit that measures the pulse width of the widened fractional pulse using a clock pulse and outputs a measurement signal of the difference between the two pulse widths, and a first read-only memory that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal. and a first converting the converted digital frequency signal into an analog voltage signal.
a digital-to-analog conversion circuit, and a voltage signal obtained by reducing the analog amount of the voltage signal by a predetermined multiple.
a reduction circuit that outputs V ₁₀ ; and a main pulse generator that generates a main pulse that rises when the first fractional pulse falls and falls when the second fractional pulse falls, based on the first and second fractional pulses. a main pulse width measuring circuit that receives the main pulse and the clock pulse, measures the pulse width of the main pulse using the clock pulse, and outputs a measurement signal;
a second read-only memory that takes the reciprocal value of the output signal of the main pulse width measurement circuit and converts it into a frequency signal; and converts the digital frequency signal converted by the second read-only memory into an analog voltage signal. A second digital-to-analog conversion circuit for converting to V ₂₀ and an addition circuit for adding analog amounts of both the voltage signals V ₁₀ and V ₂₀ and outputting a voltage signal proportional to the rotational speed of the rotating body. It is characterized by

Further, the second invention of the present application converts a sinusoidal signal having a frequency corresponding to the rotational speed output from the resolver into a square wave signal by a waveform shaping circuit,
In a rotational speed detection circuit using a resolver that measures the pulse width of the square wave signal using a clock pulse output from a clock pulse generation circuit and outputs a voltage signal corresponding to the rotational speed of a rotating body based on the measured value. , a fractional pulse P ₁ having a pulse width ΔT ₁ that receives the square wave signal and the clock pulse, rises at the rising edge of the square wave signal, and falls at the rising edge of the first clock pulse input thereafter, and a falling edge of the square wave signal. A fractional pulse P 2 having a pulse width ΔT ₂ that rises at the rising edge of the first clock pulse input thereafter and falls at the rising edge of the first clock pulse input thereafter is generated, and each of _{the fractional pulses P 1 ,} P ₂
A first fractional pulse having a pulse width (ΔT ₁ + _mTc ) and _a pulse width (ΔT ₂ +mTc); and first and second fractional pulses that receive the first and second fractional pulses and expand the pulse width of each fractional pulse by a predetermined multiple. a pulse width expansion circuit that outputs the second widened fractional pulse; and a pulse width expansion circuit that receives the first and second widened fractional pulses and the clock pulse, measures the pulse width of each widened fractional pulse using the clock pulse, and measures the difference between the two pulse widths. a first read-only memory that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal; and a first read-only memory that converts the converted digital frequency signal into an analog voltage signal. First digital-
an analog conversion circuit; a reduction circuit that outputs a voltage signal _V10 obtained by reducing the analog amount of the voltage signal by a predetermined multiple; a main pulse generating circuit that generates a main pulse that rises at the rising edge of a clock pulse and falls at the rising edge of the first clock pulse that is input after the falling edge of the square wave signal; a main pulse width measurement circuit that measures using a clock pulse and outputs a measurement signal; a second read-only memory that takes a reciprocal value of the output signal of the main pulse width measurement circuit and converts it into a frequency signal; a second digital-to-analog conversion circuit that converts _the digital frequency signal converted by the only memory into _{an analog voltage signal V 20 ;} The invention is characterized in that it includes an addition circuit that outputs a voltage signal proportional to the rotational speed of the motor.

[Operation of the Invention] The present invention detects the rotational speed of a rotating body by measuring the pulse width T ₀ of a square wave signal P ₀ obtained based on the output of a resolver using a clock pulse Pc. Based on the wave signal P ₀ and the clock pulse Pc, the first fractional pulse P ₁ ,
A second fractional pulse P ₂ and a main pulse Pm are generated respectively, and the pulse widths ΔT ₁ , ΔT ₂ , Tm of these pulses P ₁ , P ₂ , Pm are set to the period of the clock pulse Pc.
The rotation speed is detected with high precision by measuring Tc as a scale and calculating and measuring the pulse width T ₀ from each measurement value.

That is, from Figure 1, ΔT=ΔT ₂ −ΔT ₁ ...(1) Tm=n・Tc (however, n is a positive integer) ...(2) =T ₀ +ΔT ...(2') However, 0≦ΔT≦Tc From formula (2′), T ₀ =Tm−ΔT ...(3) From formulas (1), (2), and (3), T ₀ =n・Tc−(ΔT ₂ −ΔT ₁ ) = n・Tc + (ΔT ₁ − ΔT ₂ ) ...(4) In the above equation (4), n・Tc is the clock pulse
Since it is n times the period Tc of Pc, it can be measured accurately and easily. Therefore, in equation (4),
If the pulse widths ΔT ₁ and ΔT ₂ can be accurately measured, the pulse width T ₀ can be accurately measured. In the present invention, the pulse width ΔT ₁ , ΔT ₂
In order to accurately measure the pulse width, these pulse widths are once expanded by a predetermined ratio, and the expanded pulse width is measured using the period Tc of the clock pulse Pc as a measure to obtain a measurement specific signal. By reducing the measurement signal by this amount, accurate measurement values of the pulse widths ΔT ₁ and ΔT ₂ are obtained, and the pulse width T ₀ is accurately measured.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention, in which the resolver 1 outputs a sinusoidal signal S having a frequency corresponding to the rotational speed of a rotating body (not shown). The frequency f ₀ of this signal S is expressed by the following equation.

f ₀ = f _i ±Δf ...(5) Δf = N・P/120 ...(6) However, f _i : Frequency of input signal of resolver 1 (Hz) N: Rotational speed of rotating body (rpm) P : Number of poles of resolver 1 Therefore, the rotational speed N of the rotating body can be detected based on the above equations (5) and (6).

The above sinusoidal signal S is converted by the waveform shaping circuit 2 into a square wave signal P ₀ as shown in FIG. By accurately measuring the pulse width T ₀ of this square wave signal P ₀ , the rotational speed N can be detected with high precision. This embodiment includes the following configuration in order to accurately measure the pulse width T ₀ described above.

That is, in FIG.
inputs the square wave signal P ₀ from the waveform shaping circuit 2 and the clock pulse Pc with a predetermined period Tc from the clock pulse generation circuit 4, and rises at the rising edge of the square wave signal P ₀ as shown in FIG. A first fractional pulse P ₁ with a pulse width of ΔT ₁ rises at the rising edge of the first subsequent clock pulse Pc, and ΔT rises at the rising edge of the square wave signal P ₀ and falls at the rising edge of the subsequent first clock pulse Pc. A second fractional pulse P ₂ having a pulse width of ₂ is generated.

The pulse width expansion circuit 5 outputs enlarged fractional pulses P ₁₀ and P ₂₀ which are obtained by expanding the pulse width of the fractional pulses P ₁ and P ₂ outputted from the fractional pulse generation circuit 3 to K times the pulse width, respectively. It is composed of

FIG. 3 shows the pulse width expansion circuit 5 as a well-known integrator 5.
a, and a waveform shaping circuit 5b mainly consisting of an amplitude comparator.
FIG. 4 shows the waveforms of each part. To explain the principle of pulse width expansion using these drawings, let us assume that the input signal voltage is V(t), the pulse width of the input pulse _P1 is _ΔT1 , and the output signal voltage of the integrator 5a is _V0 (t),
The pulse width of the output pulse _P10 of the waveform shaping circuit 5b is
When T ₁ , the integrator 5a charges the capacitor C with current I ₁ =V(t)/R ₁ for a period of ΔT ₁ , and T ₁
=KΔT ₁ Discharged with current I ₂ =V ₀ (t)/R ₂ . The charge on capacitor C at this time is expressed by the following equation.

Q=I ₁ ΔT ₁ = [V(t)/R ₁ ] ΔT ₁ ……(7) Q=I ₂ KΔT ₁ = [V ₀ (t)/R ₂ ] KΔT ₁ ……(8) Above (7) ), (8), I ₁ ΔT ₁ = I ₂ KΔT ₁ ...(9) Therefore, from (7), (8), (9), K=I ₁ /I ₂ = [V(t ); R ₁ ]/[V ₀ (t)/R ₂ ]=R ₂ V (t) R ₁ V ₀ (t) By the way, in general, the output signal voltage of the integrator 5a V ₀
(t) is expressed by the following formula.

V ₀ (t)=(-R ₂ /R ₁ )(1-e ^-t/CR2 )V(t) Therefore, K=R ₂ V(t)=R ₂ (1-e ^-t/CR2 ) V(t) = -1(1-e ^-t/CR2 )...(10) Since the denominator of equation (10) is smaller than 1, K and the absolute value are larger than 1. Output signal voltage of integrator 5a
V ₀ (t) has a waveform as shown in FIG. 4, and this signal voltage is shaped into a rectangular wave by the waveform shaping circuit 5b to become an output pulse _P10 . This output pulse
The pulse width T ₁ of P ₁₀ is given by the following equation.

T ₁ = KBΔT ₁ = −ΔT ₁ / (1−e ^-t/CR2 )
...(11) As is clear from the fact that the absolute value of K is greater than 1 in the above equation (11), for the pulse width _{ΔT 1} of the fractional pulse P 1 input to the pulse width expansion circuit 5,
Fractional pulse output from pulse width expansion circuit 5
The pulse width T ₁ of P ₁₀ will be expanded.

The subtraction circuit 6 inputs each widened fractional pulse P ₁₀ , P ₂₀ output from the pulse width expansion circuit 5 and the clock pulse Pc from the clock pulse generation circuit 4, and calculates the pulse width of the pulse P ₁₀ using the period Tc of the clock pulse Pc as a measure. T ₁ = KΔT ₁ and pulse width
The pulse width T ₂ =KΔT ₂ of P ₂₀ is measured, the pulse width of the difference T ₁ −T ₂ =K(ΔT ₁ −ΔT ₂ ) between the respective pulse widths is calculated, and the measurement signal Pa is output.

The read-only memory (hereinafter referred to as ROM) 7 takes the reciprocal value of the pulse width K (ΔT ₁ −ΔT ₂ ) based on the measurement signal Pa, and has a digital weight corresponding to the pulse width. frequency signal
Output F ₁ .

A digital-to-analog conversion circuit (hereinafter referred to as a D/A conversion circuit) 8 receives the above frequency signal F ₁ as input, and outputs a voltage signal V ₁ having a voltage value corresponding to the digital amount of the frequency signal F ₁ . .

The reduction circuit 9 receives the above voltage signal V ₁ as input,
A voltage signal V ₁₀ is output by reducing the voltage value of the voltage signal V ₁ by a predetermined multiple.

On the other hand, the pulse generation circuit 10 receives each fractional pulse P ₁ and P ₂ from the fractional pulse generation circuit 3 as input,
A main pulse Pm is generated which rises when the first fractional pulse _P1 falls and falls when the second fractional pulse _P2 falls.

The main pulse width measurement circuit 11 uses the above main pulse Pm.
and clock pulse Pc as input, main pulse Pm
The pulse width Tm of the clock pulse Pc is measured using the period Tc of the clock pulse Pc as a measure, and a measurement signal Pb is output.

The ROM 12 calculates the reciprocal value of the pulse width Tm based on the measurement signal Pb, and outputs a frequency signal _F2 having a digital amount corresponding to the pulse width T.

The D/A conversion circuit 13 receives the frequency signal F ₂ described above and outputs a voltage signal V ₂₀ having a voltage value corresponding to the digital amount of the frequency signal F ₂ .

The addition circuit 14 receives the voltage signal V ₁₀ from the reduction circuit 9.
voltage value and the voltage signal from the D/A conversion circuit 13
By adding the voltage value of V ₂₀ , a voltage signal V ₀ having a voltage value proportional to the rotational speed of the rotating body is output.

Next, a main part of another embodiment of the present invention will be described with reference to FIG. 5, in which the configurations of the fractional pulse generation circuit and the main pulse generation circuit in the above-described embodiment are modified. The pulse widths ΔT ₁ and ΔT ₂ of each fractional pulse P ₁ and P ₂ outputted from the fractional pulse generation circuit 3 mentioned above are as follows:
All of them are in the range below the period Tc of the clock pulse Pc, but if these pulse widths are minute, the pulse width expansion circuit 5 adjusts each fractional pulse P ₁ ,
It becomes technically difficult to integrate P ₂ and expand the width of each pulse. Therefore, in the embodiment shown in FIG. 5, the fractional pulse generation circuit _{3 '} has _a time width _mTc ( (m is a positive integer, Tc is the period of the clock pulse), and is configured to output fractional pulses P ₁ ′ and P ₂ ′ with pulse widths of (ΔT ₁ +mTc) and (ΔT ₂ +mTc), respectively. ing. In the embodiment shown in FIG. 5, the main pulse generating circuit 10' receives the square wave signal from the waveform shaping circuit 2.
_p0 and the clock pulse Pc from the clock pulse generation circuit ₄ , as shown in FIG.
It is configured to generate a main pulse Pm that falls at the rising edge of the first clock pulse Pc input after the falling edge of the square wave signal _P0 . The parts of this embodiment other than those mentioned above are the same as those of the embodiment shown in FIG. 2, and related main parts are indicated by the same reference numerals.

The fractional pulses P ₁ ′, P ₂ ′ outputted from the fractional pulse generation circuit 3 ′ have their respective pulse widths expanded by K times by the pulse width expansion circuit 5, and are respectively K(ΔT ₁ +mTc) or ( The pulses are output as widened fractional pulses P ₁₀ ′ and P ₂₀ ′ with a pulse width of ΔT ₂ +mTc). The subtraction circuit 6 receives these fractional pulses and the clock pulse Pc, calculates the difference K (ΔT ₁ -ΔT ₂ ) between the respective pulse widths, and outputs a measurement signal Pa, similarly to the embodiment of FIG. Thereafter, a voltage signal corresponding to the rotational speed is obtained in the same manner as in the embodiment shown in FIG.

[Effects of the Invention] As described above, the rotational speed detection circuit of the present invention, when measuring the pulse width of the square wave signal obtained based on the output of the resolver using a clock pulse, can measure the pulse width as an integral multiple of the period. Since the fractional pulse width that inevitably occurs in addition to the main pulse width is first expanded by the pulse width expansion circuit and then measured, the fractional pulse width can be measured with high precision. Then, a voltage signal is obtained based on the measured value of this fractional pulse width, and the voltage signal is reduced by the enlarged amount, and a voltage signal is obtained based on the reduced voltage signal and the measured value of the main pulse width. Since the voltage signal is added to the voltage signal to obtain a voltage signal that corresponds to the rotation speed of the rotating body, the pulse width of the square wave signal obtained based on the output of the resolver can be measured with high precision to obtain an accurate A measurement signal can be obtained. Therefore, according to the present invention, the rotational speed of the rotating body can be detected with high accuracy.

Further, according to the invention of claim 2, when expanding the pulse width of the fraction, a time width that is an integral multiple of the period of the clock pulse is added to the pulse width of the fraction. Even if the pulse width of the fractional number is minute, the pulse width can be easily expanded, and the pulse width of the fractional number can be easily measured.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram for explaining the operating principle of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a specific configuration of the pulse width expansion circuit in FIG. 2. An example circuit diagram, Figure 4 is
FIG. 5 is a waveform diagram showing the signal waveforms of the main parts of the circuit shown in the figure, and FIG. 5 is a block diagram showing the main parts of another embodiment of the present invention. 1... Resolver, 2... Waveform shaping circuit, 3,
3'... Fractional pulse generation circuit, 4... Clock pulse generation circuit, 5... Pulse width expansion circuit, 6...
Subtraction circuit, 7, 12...ROM, 8, 13...
D/A conversion circuit, 9... Reduction circuit, 10, 10'
...Main pulse generation circuit, 11...Main pulse width measurement circuit, 14...Addition circuit.

Claims (1)

[Claims] 1. A sine wave signal having a frequency corresponding to the rotational speed output from a resolver is converted into a square wave signal by a waveform shaping circuit, and the pulse width of the square wave signal is output from a clock pulse generation circuit. In a rotational speed detection circuit using a resolver that measures using a clock pulse and outputs a voltage signal corresponding to the rotational speed of the rotating body based on the measured value, the square wave signal is detected in response to the square wave signal and the clock pulse. a first fractional pulse having a pulse width that rises at the rising edge of the square wave signal and falls at the rising edge of the first clock pulse inputted thereafter; and a first fractional pulse having a pulse width that rises at the falling edge of the square wave signal and falls at the rising edge of the first clock pulse inputted thereafter; a fractional pulse generation circuit that generates a second fractional pulse having a pulse width; and first and second fractional pulses that receive the first and second fractional pulses and expand the pulse width of each fractional pulse by a predetermined multiple. a pulse width expansion circuit that outputs a widened fractional pulse; and a pulse width expansion circuit that receives the first and second widened fractional pulses and a clock pulse, measures the pulse width of each widened fractional pulse using a clock pulse, and generates a measurement signal of the difference between the two pulse widths. a first read-only memory that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal; and a first read-only memory that converts the converted digital frequency signal into an analog voltage signal. 1 digital-to-analog conversion circuit; a reduction circuit that outputs a voltage signal _V10 obtained by reducing the analog amount of the voltage signal by a predetermined multiple; and a first fractional pulse based on the first and second fractional pulses. a main pulse generating circuit that generates a main pulse that rises at the falling edge of the second fractional pulse and falls at the falling edge of the second fractional pulse; a main pulse width measurement circuit that outputs, a second read-only memory that takes the reciprocal value of the output signal of the main pulse width measurement circuit and converts it into a frequency signal;
The digital frequency signal converted by the second read-only memory is converted into an analog voltage signal.
A second digital-to-analog conversion circuit for converting to V ₂₀ and an addition circuit for adding analog amounts of both the voltage signals V ₁₀ and V ₂₀ and outputting a voltage signal proportional to the rotational speed of the rotating body. A rotational speed detection circuit using a resolver characterized by the following. 2 Convert a sinusoidal signal with a frequency corresponding to the rotational speed output from the resolver into a square wave signal by a waveform shaping circuit, and measure the pulse width of the square wave signal using the clock pulse output from the clock pulse generation circuit. In a rotational speed detection circuit using a resolver that outputs a voltage signal corresponding to the rotational speed of the rotating body based on the measured value, upon receiving the square wave signal and the clock pulse, A fractional pulse _P1 having a pulse width ΔT ₁ that falls at the rising edge of the first input clock pulse and a pulse width ΔT ₂ that rises at the falling edge of the square wave signal and falls at the rising edge of the first input clock pulse thereafter. A fractional pulse P ₂ is generated, and a time width m (positive integer) times the period Tc of the clock pulse is added to the pulse width ΔT ₁ , _{ΔT 2 of} each fraction pulse P ₁ , P 2 . Pulse width (ΔT ₁ +
a fractional pulse generating circuit that generates a first fractional pulse with a pulse width (ΔT ₂ +mTc) and a second fractional pulse with a pulse width (ΔT 2 +mTc); a pulse width expansion circuit that outputs first and second widened fractional pulses each having a pulse width expanded by a predetermined multiple; a subtraction circuit that measures the width using a clock pulse and outputs a measurement signal of the difference between the two pulse widths; a first read-only memory that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal; a first digital-to-analog conversion circuit that converts a frequency signal of digital quantity into a voltage signal of analog quantity; a reduction circuit that outputs a voltage signal _V10 obtained by reducing the analog quantity of the voltage signal by a predetermined multiple; a main pulse that generates a pulse that rises at the rising edge of the first clock pulse inputted after the rising edge of the square wave signal and falls at the rising edge of the first clock pulse inputted after the falling edge of the square wave signal based on the square wave signal and the clock pulse; a generation circuit, a main pulse width measurement circuit that receives the main pulse and a clock, measures the pulse width of the main pulse using a clock pulse, and outputs a measurement signal; and a reciprocal value of the output signal of the main pulse width measurement circuit. a second read-only memory that converts the frequency signal into a frequency signal; and a second digital-to-analog conversion circuit that converts the digital frequency signal converted by the second read-only memory into an analog voltage signal _V20 . A rotation speed detection circuit using a resolver, comprising: an addition circuit that adds analog quantities of both voltage signals V ₁₀ and V ₂₀ and outputs a voltage signal proportional to the rotation speed of a rotating body.