JPS614966A - Rotating speed detecting circuit using resolver - Google Patents

Abstract

PURPOSE:To detect the rotating speed of a rotating body with high precision by expanding and measuring a terminal number pulse width by a pulse width expanding circuit when measuring the pulse width of a rectangular wave signal obtained on the basis of a resolver. CONSTITUTION:The output of the resolver 1 is inputted to a terminal number pulse generating circuit 3 through a waveform shaping circuit 2 and the 1st and the 2nd terminal number pulses outputted by this terminal number pulse generating circuit 3 are inputted to a main pulse generating circuit 10 and the pulse width expanding circuit 5. Further, a main pulse outputted by the main pulse generating circuit 10 is supplied to a main pulse width measuring circuit 11 and a digital value is red out of an ROM12 according to the output of the circuit 11 and supplied to an adding circuit 14 through a D/A converter 13. A pulse having pulse width expanded by the pulse width expanding circuit 5, on the other hand is supplied to a subtracting circuit 6 and a digital value is read out of an ROM7 with the output of the circuit 6 and supplied to the adding circuit 14 through a D/A converter 8 and a reducing circuit 9.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] The present invention is a rotational speed detection circuit using a resolver, and in particular, a method for detecting a rotating body based on a sine wave signal having a frequency corresponding to the rotational speed output from the resolver. This invention relates to a circuit that detects rotational speed.

[Prior art] Many resolvers have been used as position detectors in machine tools, and among them, brushless resolvers are widely used as position detectors in numerical control mechanisms because they are highly accurate and can rotate at high speeds. It's here. In addition, in recent years,
Resolvers have also been used as speed detectors. Now, if the rotation angle of the resolver at time t1 is θ1, and the rotation angle at time t2 is shifted from θ2, then (θ2
−〇+)/(t2/t+) is the change in rotation angle per unit time. Therefore, the rotational speed of the rotating body can be detected by measuring the change per unit time in the arbitrary rotation angle θ of the sinusoidal signal output from the resolver.

However, this method of detecting the rotational speed by directly utilizing the sinusoidal signal output from the resolver has the disadvantage that highly accurate detection cannot be performed. The reason for this is that during one revolution of the resolver, there is always one point where the resolver origin, that is, the phase of the input signal and the output signal match, and the rotation angle θ is measured with this resolver origin as a reference. However, due to the characteristics of resolvers, there is discontinuity in the input/output relationship near the resolver origin, so it is not possible to accurately measure the rotation angle θ from the resolver origin, and as a result, the rotation speed cannot be measured with high accuracy. This means that it cannot be detected.

[Problems to be Solved by the Invention] Therefore, a square wave signal Po as shown in FIG. 1 is obtained based on the output of the resolver, a clock pulse Pc is obtained by a pulse generation circuit, and the square wave signal Po is Pulse width To
It has been considered to detect the rotational speed of the rotating body by measuring the period of the clock pulse pc as a measure.

In this case, the above pulse width Ta is the clock pulse Pc
The shorter the period TC, the more accurate the measurement can be, but since the rising and falling times of the square wave signal PO do not coincide with the rising and falling times of the clock pulse pc, the clock pulse Pc No matter how short the period TC is, fractions of the time widths ΔT+ and ΔT2 will occur near the rise and fall of the square wave signal Pa, and if this continues, the pulse width To
cannot be measured accurately, and the rotational speed cannot be detected with high precision.

[Object of the Invention] An object of the present invention is to provide a rotational speed detection circuit using a resolver that can detect the rotational speed of a rotating body with high precision using a resolver as a detection element.

[Means for solving the problem] In order to solve the above-mentioned problem, the first invention of the present application includes the following:
A sine wave signal with a frequency corresponding to the rotational speed output from the resolver is converted into a square wave signal by a waveform shaping circuit, and the pulse width of the square wave signal is changed using the clock pulse output from the clock pulse generation circuit. In a rotation speed detection circuit using a resolver that measures the voltage signal and outputs a voltage signal corresponding to the rotation speed of the rotating body based on the measured value, upon receiving the square wave signal and the clock pulse, at the rising edge of the square wave signal. The first clock pulse has a pulse width that falls at the rising edge of the first clock pulse input after the rising edge.
and a second fractional pulse having a pulse width that rises at the falling edge of the square wave signal and falls at the rising edge of the first clock pulse input thereafter; a pulse width expansion circuit that receives a second fractional pulse and outputs first and second widened fractional pulses in which the pulse width of each fractional pulse is expanded by a predetermined multiple; and the first and second widened fractional pulses. and a subtraction circuit that receives a clock pulse, measures the pulse width of each widened fractional pulse using a clock pulse, and outputs a measurement signal of the difference between the two pulse widths, and a subtraction circuit that takes the reciprocal of the output signal of the subtraction circuit and converts it into a frequency signal. a first read-only memory for conversion, a first digital-to-analog conversion circuit for converting the converted digital frequency signal into an analog M voltage signal, and a reduction in the analog range of the voltage signal by a predetermined multiple. a reduction circuit that outputs a voltage signal 1o, and generates a main pulse that rises when the first fractional pulse falls and falls when the second fractional pulse falls, based on the first and second fractional pulses; a main pulse generation circuit, a main pulse width measurement circuit that receives the main pulse and the clock pulse, measures the pulse width of the main pulse using the clock pulse, and outputs a measurement signal; a second read-only memory that takes an inverse @ value and converts it into a frequency signal; and a second digital - that converts the digital frequency signal converted by the second read-only memory into an analog voltage signal V20. An analog conversion circuit and both voltage signals Vl [l, V2
The present invention is characterized in that it includes an addition circuit that adds up the amount of logs of O and outputs a voltage signal proportional to the rotational speed of the rotating body.

Further, the second invention of the present application converts a sinusoidal signal having a frequency corresponding to the rotational speed output from the resolver into a square wave signal by a waveform shaping circuit, and uses the pulse width of the square wave signal to generate a clock pulse. In a rotation speed detection circuit using a resolver that measures using a clock pulse output from the circuit and outputs a voltage signal according to the rotation speed of a rotating body based on the measured value, the square wave signal and the clock pulse are used. A fractional pulse P1 having a pulse width ΔT1 that rises at the rising edge of the square wave signal and falls at the rising edge of the first clock pulse input thereafter; Each fractional pulse P+ is generated by generating a fractional pulse P2 having a pulse width ΔT2 that falls at the rising edge of the clock pulse.

A first pulse having a pulse width (ΔT 1 + m T c ) by adding a time width m (positive integer) times the period Tc of the clock pulse to the pulse widths ΔT+ and ΔT2 of P2, respectively.
a fractional pulse generating circuit that generates a fractional pulse and a second fractional pulse having a pulse width (ΔT2+mTc); a pulse width expansion circuit that outputs first and second widened fractional pulses expanded by a predetermined multiple;
a subtraction circuit that receives the first and second widened fractional pulses and a clock pulse, measures the pulse width of each widened fractional pulse using the clock pulse, and outputs a measurement signal of the difference between both pulse widths; and an output of the subtraction circuit. a first read-only memory that takes a reciprocal value of a signal and converts it into a frequency signal; a first digital-to-analog conversion circuit that converts the converted digital frequency signal into an analog voltage signal;
a reduction circuit that outputs a voltage signal 1o obtained by reducing the analog amount of the voltage signal by a predetermined multiple; and a rising edge of the first clock pulse that is input after the rising edge of the square wave signal based on the square wave signal and the clock pulse. a main pulse generating circuit that generates a main pulse that rises at the same time and falls at the rise of the first clock pulse that is input after the fall of the square wave signal; and a main pulse generating circuit that receives the main pulse and the clock pulse and clocks the pulse width of the main pulse. A main pulse width measurement circuit that measures pulses and outputs a measurement signal;
a second read-only memory that takes the reciprocal value of the output signal of the main pulse width measuring circuit and converts it into a frequency signal; and a second read-only memory that converts the digital frequency signal converted by the second read-only memory into an analog voltage signal. a second digital-to-analog converter circuit for converting into V20, and an addition circuit for adding analog amounts of both voltage signals Vlo and V2'D to output a voltage signal proportional to the rotational speed of the rotating body. It is characterized by the following:

[Operation of the Invention] The present invention detects the rotational speed of a rotating body by measuring the pulse width To of a square wave signal Pa obtained based on the output of a resolver using a pulse PC.
Based on the square wave signal Po and the clock pulse PC, a first fractional pulse P+, a second fractional pulse P2 and a main pulse Pm are generated, respectively, and these pulses Pl
, each pulse width ΔT+, ΔT2 . Tmori 0
The rotation speed is detected with high precision by measuring the period TC of the pulse Pc as a measure and calculating and measuring the pulse width To from each measurement value.

That is, from Figure 1, ΔT-ΔT2-ΔT1...(1)
Tm=n-Tc (where n is a positive integer)-=(2)-T
o+ΔT...(2°) However, 0
≦ΔT≦TC From formula (2゛), To = Tm - 8T - (3) (
1), (2>, and (3), To-n-TC-(ΔT2-ΔT1) =n-Tc+ (ΔT+-ΔT2) −(4) Above (
In equation 4), n-Tc is n times the period Tc of the clock pulse PC, so it can be measured accurately and easily. Therefore, in equation (4), the pulse width ΔT+,
If ΔT2 can be measured accurately, the pulse width TO
can be measured accurately. In the present invention, in order to accurately measure the pulse widths ΔT+ and ΔT2, these pulse widths are once expanded by a predetermined ratio, and the expanded pulse width is measured using the period TO of the clock pulse Pc as a measurement signal. Then, by reducing the measurement signal by the enlarged amount, accurate measurement values of the pulse widths ΔT+ and ΔT2 are obtained, and the pulse width To is accurately measured.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of an embodiment of the present invention, in which the resolver 1 outputs a sinusoidal signal S having a frequency corresponding to the rotational speed of a rotating body (not shown). The frequency f of this signal S is expressed by the following equation.

f, = f, ±△f ... (5
)Δf=NP/120...
(6) However, fi: Frequency of input signal of resolver 1 (R
7,) N: Rotational speed (rpm) of the rotating body P: Number of poles of the resolver 1 Therefore, the rotational speed N of the rotating body can be detected based on the above equations (5) and (6).

The above sinusoidal signal S is converted by the waveform shaping circuit 2 into a square wave signal PO as shown in FIG. By accurately measuring the pulse width To of this square wave signal Pa, the rotational speed N can be detected with high precision. This embodiment has the following configuration in order to accurately measure the above pulse width To.

That is, in FIG. 2, the fractional pulse generation circuit 3 receives the square wave signal Pa and clock pulse from the waveform shaping circuit 2, and the clock pulse 2P having a predetermined period TC from the generation circuit 4.
A first fractional pulse P1 having a pulse width of ΔT1 which rises at the rise of the square wave signal MPo and falls at the rise of the first clock pulse Pc thereafter, as shown in FIG. A second fractional pulse P2 having a pulse width of ΔT2 is generated which rises at the falling edge of the wave signal Po and falls at the subsequent rising edge of the first clock pulse Pc.

The pulse width expansion circuit 5 generates widened fractional pulses P10, which are obtained by expanding the pulse widths of the respective fractional pulses PI and P2 outputted from the fractional pulse generation circuit 3 to twice the pulse width, respectively.
P2o].

FIG. 3 shows an example in which the pulse width expansion circuit 5 is configured using a well-known integrator 5a and a waveform shaping circuit 5b mainly consisting of an amplitude comparator, and FIG. 4 shows the waveforms of each part. It is something. To explain the principle of pulse width expansion using these drawings, let us now assume that the input signal voltage is V(t) and the input pulse P1.
The pulse width of is 8T1, and the output signal voltage of the integrator 5a is V.

(t), when the pulse width of the output pulse P10 of the waveform shaping circuit 5b is T1, the integrator 5a charges the capacitor C with the current 1+-V(t)/R+ for a period of ΔT1, and T+
In the period of ΔT1, the current T>-Vn (t)
/R2 to discharge. The charge on capacitor C at this time is expressed by the following equation.

Q=1+ΔT+=(V(t)/R+)8T1・
...(7) Q=I2 and ΔT+ = (Va (t)/R
2) KΔT1...(8) From equations (7) and (8) above, 11ΔTI=ΔT1 to I2...(9) Therefore, from equations (7), (8'), and (9), K= II/1
2-(V('t)/R+)/('VD(t)/R2
) = R2V(t)/R+ Vo (t) By the way,
Generally, the output signal voltage V of the integrator 5a.

([) is expressed by the following formula.

Vo (j:,,)=(-R2/R+ 01-e'
”CR2) V (t) Therefore, -t/CL K=R2V(j)/-R2(1-e) V(
t)=-1/[1-e """2),
(10) Since the denominator of equation (10) is smaller than 1, the absolute value of K is larger than 1. Output signal voltage V of integrator 5a
o(t) has a waveform as shown in FIG. 4, and this signal voltage is shaped into a rectangular wave by the waveform shaping circuit 5b to become the output pulse PIo. The pulse width T1 of this output pulse P+6 is given by the following equation.

T+"KΔT1-1ΔT+/(1-e-"CR2
)...(11) As is clear from the fact that the absolute value of K is greater than 1 in the above equation (11), the pulse width ΔT+ of the fractional pulse P1 input to the pulse width expansion circuit 5 is The pulse width T1 of the fractional pulse PIO output from the width expansion circuit 5 is expanded.

The subtraction circuit 6 inputs each widened fractional pulse Pl[+, P2Q outputted from the pulse width widening circuit 5 and the clock pulse Pc from the clock pulse generation circuit 4, and calculates the pulse PIO using the period TC of the clock pulse Pc as a measure. Measure ΔT1 for the pulse width T+'= and ΔT2 for the pulse width T2= of pulse P20, and calculate the difference T between each pulse width.
The pulse width of + -T2 =K (ΔT1-ΔT2) is calculated and the measurement signal pa is output.

Read-only memory (hereinafter abbreviated as RC) 7
is the above pulse width K〈Δ based on the above measurement signal pa
The reciprocal value of T1-ΔT2) is taken and a frequency signal F1 having a digital amount corresponding to the pulse width is output.

A digital-to-analog conversion circuit (hereinafter referred to as a D/A conversion circuit) 8 receives the above-mentioned frequency signal F1 as input and outputs a voltage signal 1 having a voltage value chamber corresponding to the digital amount of the frequency signal F1.

The reduction circuit 9 receives the above voltage signal V1 as input, and generates a voltage signal V1 obtained by reducing the voltage value of the voltage signal 1 by a predetermined multiple.
Outputs 0.

On the other hand, the main pulse generating circuit 10 receives each fractional pulse P1 . P2 is input, and a main pulse pm is generated which rises when the first fractional pulse P1 falls and falls when the second fractional pulse P2 falls.

The main pulse width measurement circuit 11 uses the above main pulse Pm and
The input pulse is PCt, and the pulse width T of the main pulse P amount is
m is measured using the period TC of the clock pulse pc as a measure, and a measurement signal Pb is output.

The ROM 12 calculates the reciprocal value of the pulse width T amount based on this measurement signal pb, and outputs a frequency signal F2 having a digital amount corresponding to the pulse width Tm.

The D/A conversion circuit 13 receives the frequency signal F2 as input and outputs a voltage signal V2'[+ having a voltage value corresponding to the digital amount of the frequency signal F2.

The adder circuit 14 adds the voltage value of the voltage signal V IQ from the reduction circuit 9 and the voltage value of the voltage signal V20 from the D/A converter circuit 13 to obtain a voltage value proportional to the rotational speed of the rotating body. Outputs voltage signal Vo.

Next, a main part of another embodiment of the present invention will be described with reference to FIG. 5, in which the configurations of the fractional pulse generation circuit and the main pulse generation circuit in the above-mentioned embodiment are modified. The pulse widths ΔT+ and ΔT2 of each fractional pulse PI and P2 outputted from the fractional pulse generation circuit 3 mentioned above are all equal to the clock pulse PC.
However, if these pulse widths are minute, it is technically difficult to integrate each fractional pulse PI, P2 in the pulse width expansion circuit 5 to expand each pulse width. Become. Therefore, in the embodiment shown in FIG.
The fractional pulse generation circuit 3' adds a time width mTc (m is a positive integer, TO is the period of the clock pulse) to each pulse width ΔT+, ΔT2 of the fractional pulses PI and P2 generated as described above. , fractional pulses P+ with pulse widths of (ΔT++mTC> and (ΔT2 +mTC), respectively)
', P2'. Also the fifth
In the illustrated embodiment, the main pulse generation circuit 10' inputs the square wave signal Pa from the waveform shaping circuit 2 and the clock pulse PC from the clock pulse generation circuit 4, and generates a square wave signal as shown in FIG. It is configured to generate a main pulse pm which rises at the rise of the first clock pulse pc input after the rise of PO and falls at the rise of the first clock pulse Pc input after the fall of the square wave signal Pa. . The parts of this embodiment other than those mentioned above are the same as those of the embodiment shown in FIG. 2, and related main parts are indicated by the same reference numerals.

The fractional pulses PI' and P2' outputted from the fractional pulse generation circuit 3' are expanded to twice their respective pulse widths by the pulse width expansion circuit 5, and are respectively K(ΔT
++mTC) or K(ΔT20m7-c) as widened fractional pulses PIG', P21]'. The subtraction circuit 6 receives these fractional pulses and the clock pulse pc, calculates the difference K (ΔT1-ΔT2) between the respective pulse widths, and outputs the measurement signal pa, similarly to the embodiment of FIG. Thereafter, a voltage signal corresponding to the rotational speed is obtained in the same manner as in the embodiment shown in FIG.

[Effects of the Invention] As described above, the rotational speed detection circuit of the present invention, when measuring the pulse width of the square wave signal obtained based on the output of the resolver using a clock pulse, can measure the pulse width as an integral multiple of the period. Since the fractional pulse width that inevitably occurs somewhere in the main pulse width is first expanded by the pulse width enlarging circuit and then measured, the fractional pulse width can be measured with high precision. Then, a voltage signal is obtained based on the measured value of this fractional pulse width, and the voltage signal is reduced by the enlarged amount, and a voltage signal is obtained based on the reduced voltage signal and the measured value of the main pulse width. Since the voltage signal is added to the voltage signal and the voltage signal is determined according to the rotational speed of the rotating body, the pulse width of the square wave signal obtained based on the output of the resolver can be measured with high precision. It is important to obtain accurate I11 constant signal tone. Therefore, according to the present invention, the rotational speed of the rotating body can be detected with high accuracy.

Further, according to the invention of claim (2), when the pulse width of the fractional number is expanded, a time width that is an integral multiple of the period of the clock pulse is added to the pulse width of the fractional number. Therefore, even if the pulse width of the fractional number is minute, the pulse width can be easily expanded, and the pulse width of the fractional number can be easily measured.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram for explaining the operating principle of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a specific configuration of the pulse width expansion circuit in FIG. 2. FIG. 4 is a waveform diagram showing signal waveforms of the main parts of the circuit of FIG. 3, and FIG. 5 is a block diagram showing the main parts of another embodiment of the present invention.

Claims (2)

[Claims] (1) A sine wave signal with a frequency corresponding to the rotational speed output from the resolver is converted into a square wave signal by a waveform shaping circuit, and the pulse width of the square wave signal is converted into a clock pulse output from a clock pulse generation circuit. Measured using
In a rotational speed detection circuit using a resolver that outputs a voltage signal corresponding to the rotational speed of the rotating body based on the measured value, the voltage signal is inputted when the square wave signal and the clock pulse are received at the rising edge of the square wave signal. a first fractional pulse having a pulse width that falls at the rising edge of the first clock pulse inputted, and a pulse width that rises at the falling edge of the square wave signal and falls at the rising edge of the first clock pulse input thereafter; a fractional pulse generation circuit that generates a second fractional pulse; and first and second widened fractional pulses that expand the pulse width of each fractional pulse by a predetermined multiple in response to the first and second fractional pulses; a subtraction circuit that receives the first and second widened fractional pulses and the clock pulse, measures the pulse width of each widened fractional pulse using the clock pulse, and outputs a measurement signal of the difference between the two pulse widths; circuit, and a first circuit that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal.
a read-only memory, a first digital-to-analog conversion circuit that converts the converted digital frequency signal into an analog voltage signal, and a voltage signal V_1_0 obtained by reducing the analog value of the voltage signal by a predetermined multiple. and a main pulse generation circuit that generates a main pulse that rises when the first fractional pulse falls and falls when the second fractional pulse falls, based on the first and second fractional pulses. , a main pulse width measurement circuit that receives the main pulse and the clock pulse, measures the pulse width of the main pulse using the clock pulse, and outputs a measurement signal; and a reciprocal value of the output signal of the main pulse width measurement circuit. a second read-only memory that converts into a frequency signal; a second digital-to-analog conversion circuit that converts the digital frequency signal converted by the second read-only memory into an analog voltage signal V_2_0; 1. A rotational speed detection circuit using a resolver, comprising an addition circuit that adds analog amounts of both voltage signals V_1_0 and V_2_0 and outputs a voltage signal proportional to the rotational speed of a rotating body. (2) A sine wave signal with a frequency corresponding to the rotational speed output from the resolver is converted into a square wave signal by a waveform shaping circuit, and the pulse width of the square wave signal is converted into a clock pulse output from the clock pulse generation circuit. Measured using
In a rotational speed detection circuit using a resolver that outputs a voltage signal corresponding to the rotational speed of the rotating body based on the measured value, the voltage signal is inputted when the square wave signal and the clock pulse are received at the rising edge of the square wave signal. Pulse width ΔT_ which falls at the rising edge of the first clock pulse
A fractional pulse P_1 having a value of 1 and a fractional pulse P_2 having a pulse width ΔT_2 that rises at the falling edge of the square wave signal and falls at the rising edge of the first clock pulse input thereafter are generated, and each fractional pulse P_1 is generated. ,
A first fractional pulse having a pulse width (ΔT_1+mTc) and a pulse width (ΔT_2+mTc) are obtained by adding a time width m (positive integer) times the period Tc of the clock pulse to the pulse widths ΔT_1 and ΔT_2 of P_2, respectively. a fractional pulse generation circuit that generates a second fractional pulse, and first and second fractional pulses that receive the first and second fractional pulses and expand the pulse width of each fractional pulse by a predetermined multiple;
a pulse width expansion circuit that outputs a widened fractional pulse; and a pulse width expansion circuit that receives the first and second widened fractional pulses and a clock pulse, measures the pulse width of each widened fractional pulse using a clock pulse, and measures the difference between both pulse widths. a subtraction circuit that outputs a signal; a first read-only memory that takes the reciprocal value of the output signal of the subtraction circuit and converts it into a frequency signal; and converts the converted digital frequency signal into an analog voltage signal. a first digital-to-analog conversion circuit that outputs a voltage signal V_1_0 that is obtained by reducing the analog amount of the voltage signal by a predetermined multiple; a main pulse generating circuit that generates a main pulse that rises at the rising edge of a first clock pulse inputted later and falls at the rising edge of the first clock pulse inputted after the falling edge of the square wave signal; a main pulse width measurement circuit that receives the main pulse, measures the pulse width of the main pulse using a clock pulse, and outputs a measurement signal;
a second read-only memory that takes the reciprocal value of the output signal of the main pulse width measuring circuit and converts it into a frequency signal; and a second read-only memory that converts the digital frequency signal converted by the second read-only memory into an analog voltage signal. The present invention is characterized by comprising a second digital-to-analog conversion circuit that converts the voltage signals V_2_0 to V_2_0, and an addition circuit that adds the analog amounts of the two voltage signals V_1_0 and V_2_0 and outputs a voltage signal proportional to the rotational speed of the rotating body. A rotation speed detection circuit using a resolver.