JPH0418721A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable the semiconductor IC in excellent efficiency to be manufactured by a method wherein the lithographic process making preparations of the wafers having elements in which the gate numbers per chip are finely sectioned with a less number of masks. CONSTITUTION:Three lines by three columns of blockes 1 as the pattern regions are arranged on a transparent e.g. quartz-made substrate 3 while spacers 2 are provided between respective blocks 1. When these blocks 1 are used as a reticle mask, the blocks 1 in the non-applied regions (b) are shielded with a shielding means like the reticle blind of an exposure device not to be irradiated with light during transfer process. Through these process, restricted numbers of blocks 1 are used as the reticle mask to set up the repeated transfer gaps corresponding to the size of applied regions (a) so that the element formed wafers in various gate numbers may be manufactured by arranging only one set of masks.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to lithography processing of gate arrays, and aims to provide a mask pattern transfer method that can reduce the number of types of photomasks and finely set the number of formed transistors. A semiconductor integrated circuit device to be fabricated is prepared by preparing a reticle mask in which a plurality of pattern blocks are arranged, with a pattern block in which mask patterns for forming a plurality of semiconductor active elements are arranged as a unit. Setting the number of pattern blocks corresponding to the number of semiconductor active elements to be provided, selecting the set number of pattern blocks arranged adjacent to each other in the reticle mask, and selecting the selected pattern blocks. The structure includes a step of optically transferring a reticle mask to a photosensitive film as a reticle mask for one chip.

[Industrial application field]

TECHNICAL FIELD This invention relates to gate array lithography processes, and more particularly to the use of reticle masks in fabricating transistor-prepared wafers.

In semi-custom integrated circuits (hereinafter referred to as IC) such as gate arrays, semiconductor wafers with a predetermined number of gates are prepared, and the wafers that match the customer's order are selected for internal wiring. and completing the IC.

Note that the number of gates referred to here is often the number of transistors, but there are cases where a plurality of transistors are counted as one.

(Problem to be solved by conventional technology and invention) The number of gates prepared in advance on this type of wafer is usually 1000.2000.
．． The number is 5,000 or 10,000, and is set at relatively coarse intervals. Therefore, for example 6000
When manufacturing a logic circuit IC that requires gates, a wafer with gate #1toooo must be used, and 40% of the number of gates is wasted. This results in high manufacturing costs.

In order to avoid such inconvenience, the number of gates prepared in advance on the wafer should be set to 1000.2000. ．． 3000,
The number may be divided into small sections such as 4,000 and 10,000. However, if these wafers are prepared by making masks for each type as usual, it is difficult to amortize the cost of masks for wafers with a small number of gates that are rarely used.

An example of a technique proposed as an improvement measure for redicle masks to deal with such problems is Japanese Patent Application Laid-Open No. 61-94341.
However, the invention disclosed in the published patent publication divides the pattern of a reticle mask for one chip into a gate play area and a peripheral circuit area, and divides the pattern of a reticle mask for one chip into a gate play area and a peripheral circuit area,
The purpose of this method is to form a gate array portion of a required size by repeating pattern-by-pattern transfer. At that time, the size of the peripheral circuit section must be changed accordingly, but a divided reticle mask is used to cope with such a situation.

According to this method, it is possible to manufacture wafers with different numbers of elements using one set of masks, but since the number of reticle masks that make up a cent increases several times compared to the usual number, the mask cost is not reduced. This cannot be expected, and the repeated transfer operation becomes complicated.

An object of the present invention is to prepare a wafer with elements formed on it, in which the number of gates for one chip is finely divided by a smaller number of masks, and to provide a lithography processing method, thereby creating a semi-custom IC with high gate utilization efficiency. The goal is to realize the following.

[Means to solve the problem]

In order to achieve the above object, in the lithography process included in the present invention, a pattern block in which a mask pattern for forming a plurality of semiconductor active elements is arranged is used as a unit, and a plurality of pattern blocks are arranged. Prepare a reticle mask, set the number of pattern flocks corresponding to the number of semiconductor active elements that a semiconductor integrated circuit device to be manufactured should have, and set the set number of pattern flocks that are arranged adjacent to each other in the reticle mask. A pattern blank is selected, and the selected mask pattern is optically transferred onto the photosensitive film as a reticle mask for one chip.

[Function] Although the mask pattern for the gate array may have different element arrangements in the logic gate part and the peripheral circuit part, as in the prior art example mentioned by Ail, the element arrangement within the chip is uniform. The ability to keep things as they are will enable us to respond to more diverse demands. This method is also adopted in the present invention, and the number of gates distributed approximately evenly within the chip is increased or decreased in units of a predetermined number.

In the present invention, a gate array pattern including a certain number of elements is used as a unit block, and the blocks arranged in a matrix are prepared as a basic reticle mask. FIG. 1 is a simplified diagram showing this. In FIG. 9A, blocks 1, which are pattern areas, are arranged in 3 rows and 3 columns on one side of a transparent substrate 3 such as quartz, and a space 4J'2 is provided between each block. 'I have been treated.

When using this as a reticle mask, use a light-shielding stage like the reticle blind of an exposure device to
As shown in α)) in the same figure, the transfer is performed in such a way that the irradiation light does not hit the knocks in the unused area.

By using such a limited block as a mask and setting the repeat transfer interval according to the size of the area to be used, it is possible to produce wafers with various gate numbers by simply preparing one set of masks. I can do things.

Due to the exposure/non-exposure division due to the reticle blind, it is inevitable that the division line will become slightly unclear,
Since a blank area of a predetermined width exists around the block, it is easy to reliably transfer the pattern within the selected block and reliably block light irradiation to non-selected areas.

Note that by reducing the number of gates in one block, the number of data in one chip can be adjusted more finely, and when arranging the selected blocks in a rectangle within the chip, the number of vertical and horizontal blocks can be adjusted more precisely. Although this is advantageous in that it allows more freedom in selecting the block L2, the blank space provided between the blocks L2 increases and the efficiency of chip area utilization decreases.

〔Example〕

FIG. 2 is a diagram showing a pattern arrangement in an embodiment of the present invention. Kogodemo 3 is a transparent substrate, 500 games 1-
Blocks 1, which are pattern areas including the above, are arranged in 6 rows and 3 columns, and spacers 2 are provided between each block. Block dimensions are 2.0mm x 1.0m
m, and the width of the spacer is 0.2+nm.

Using this as a reticle mask, each time the transfer area is limited as shown in Figure 3 (k+ (a) to x), 1000.] 500, 2000, 3000, 4
000,4500.50006000,7500 and 9
It is possible to form an IC chip with a cell count of 000. Needless to say, if the number of blocks arranged is increased, patterns including a larger number of gates can be repeatedly transferred. In this embodiment, there are two types of block arrangement of 6000 gates, and the convenient one can be selected.

At the boundary of the transfer area limited by the reticle blind, the pattern may become blurred or light may leak outside the boundary due to diffraction of the irradiated light. This is because the reticle blind was not intended for this kind of use, and if the spacer provided between the blocks is wide enough, this problem can be overcome. &J Rugotoka can do it. When repetitive transfer is performed on a chip-by-chip basis, the above-mentioned width of the spacer is sufficient because the relevant portion is included in the scribe area.

Furthermore, when a reticle blind is used to limit the area irradiated with transfer light, it is usually not easy to ensure that there is a minimum area that can be defined. In the reticle mask of this example, the minimum transferable area was 3 columns x 2 rows, that is, 3000 gates. However, this minimum area limitation is not essential, and if the transfer device has a light shielding means suitable for implementing the present invention, the area will be further reduced, and FIGS. 3(a) to (C) ), it is possible to form an IC chip with a relatively small number of gates.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to manufacture IC chips with various numbers of elements using a single readicle mask, and a situation in which mask costs cannot be amortized due to variations in frequency of use does not occur. do not have.

Therefore, it is possible to prepare gate array wafers with various numbers of gates, and it is possible to always maintain high gate utilization efficiency.

[Brief explanation of drawings]

Fig. 1 is a schematic diagram showing the block arrangement and usage pattern of the present invention, Fig. 2 is a diagram showing the block arrangement of the embodiment, and Fig. 3 is a diagram showing the usage pattern in the embodiment. 1 is a block which is an element formation region, 2 is a spacer, and 3 is a transparent substrate. ■ (e) 4000 Gs (f) 4500 Gs (g) 5000 Gs (h) 6000 Gs (i) 6000 Gs (j) 7500 Gs (k) 9000 Gs

Claims (1)

[Claims] A semiconductor to be manufactured by preparing a reticle mask in which a pattern block in which a mask pattern for forming a plurality of semiconductor active elements is arranged is arranged as a unit, and in which a plurality of pattern blocks are arranged. setting a number of pattern blocks corresponding to the number of semiconductor active elements that an integrated circuit device should have, and selecting the set number of pattern blocks arranged adjacent to each other in the reticle mask; A method for manufacturing a semiconductor integrated circuit device, comprising the step of optically transferring a pattern block to a photosensitive film as a reticle mask for one chip.