JPH041884B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an accumulation time control circuit for a focus detection device that uses an accumulation type photoelectric conversion element as a light receiving sensor and detects a subject distance based on the output of the light receiving sensor.

BACKGROUND ART Focus detection apparatuses have been known that form a subject image on an accumulation type photoelectric conversion element, such as a line image sensor using a CCD, and perform focus detection based on an image signal accumulated in the element.

The storage type photoelectric conversion element described above has a narrow dynamic range with respect to the amount of light, and cannot be used as is under all brightness conditions that allow photography. A method of adjusting the signal level (automatic gain control) is used.

Further, even at the same luminance, there is a phenomenon in which the accumulated image signal is easy to detect when the contrast is strong during the focus detection operation, and difficult to detect when the contrast is weak. Furthermore, since the contrast of an image is stronger when illuminated with artificial light than with natural light, a method of illuminating an image with weak contrast with artificial light to increase the contrast may be considered. However, when the contrast is strengthened by illuminating with artificial light, the image level may become higher than necessary if the automatic gain control is performed in the same way as with natural light.

That is, in the case of an image illuminated with natural light and having weak contrast as shown in Figure 1A, if the accumulation time is controlled using the automatic gain control described above, the image signal will be amplified as shown in Figure 1A', and the image level will be lowered. is adjusted to an appropriate value, but if the above object is illuminated with artificial light and an image with a strong contrast as shown in Figure 1B is obtained, the same automatic gain control as in the case of a weak contrast case is performed. B′, and unnecessary image level widening is performed. Therefore, for images that are illuminated with artificial light and have a strong contrast, the image level will be appropriate even if the storage time is shortened, and by doing this, the storage time can be shortened and the focus detection operation can be made faster. It becomes possible to execute it in

The present invention has been made in view of the above matters, and includes a light receiving sensor comprising a storage type photoelectric conversion element that receives light flux from a subject and accumulates the received light signal, and a light receiving sensor that is accumulated in the photoelectric conversion element. a light amount regulation circuit that regulates the amount of signal accumulation to a predetermined amount;
In an autofocus device that performs arithmetic processing for autofocus based on the sensor output whose accumulation amount is regulated by the circuit and performs autofocus operation according to the calculation result, the light reception signal by the photoelectric conversion element When the accumulation operation is performed without projecting the luminous flux from the light projecting means to the subject, the accumulation amount is regulated by the light amount regulating circuit and set to a first value, while the accumulation operation is A setting circuit is provided for setting an accumulation amount regulated by the light amount regulating circuit to a second value lower than the first value when photographing a subject under the projection of a luminous flux from the light projecting means. The present invention provides an autofocus device that achieves the objective.

In the embodiment, the sensors 15 and 16 in FIG. 1 correspond to the light receiving sensor, the capacitor C, the resistors R ₁ and R ₃ , and the comparison circuit CP ₁ in FIG. 6 correspond to the light amount regulating circuit, and the switch AS and the resistor R ₂ corresponds to the setting circuit.

Next, a focus detection device to which the accumulation time control circuit according to the present invention is applied will be explained.

FIG. 2 is a configuration diagram showing the configuration of a camera system in which the focus detection device described above is employed. In the figure, 2 indicates a camera, and an image from a subject 1 is guided to a main mirror 3 having a half mirror through a photographing lens (objective lens 12) of the camera. The image passing through the half mirror is formed on the light receiving sensor section via the auxiliary mirror 4 and the focus detection optical system 5. 6 is a flash device having an auxiliary light source 8 attached to the camera 2.

FIG. 3 is a configuration diagram showing the principle configuration of the focus detection optical system shown in FIG. 1. In the figure, 13 indicates a position equivalent to the film surface, and when focusing, the lens 12
An image from the subject 1 that enters through the lens is formed at the position 13 described above. Reference numeral 14 passes through a secondary optical system, and the above image is formed on the light receiving sensors 15 and 16 of the light receiving sensor section 20 via this optical system. The light receiving sensor 15 is a sensor for a reference field of view, 16 is a sensor for a reference field of view, and the sensor 1 is a sensor for a reference field of view.
The image pattern formed on sensor 5 is focused on sensor 1 when in focus.
It matches the pattern imaged at a predetermined position on 6. Therefore, when the image is out of focus, the image pattern formed on the sensor 15 is formed at a position different from the position on the sensor 16.

FIG. 4 is a circuit diagram showing an embodiment of an automatic focus adjustment device to which the accumulation time control circuit according to the present invention is applied. In the figure, 20 is the light receiving sensor section, and 15 and 16 are the light receiving sensors, respectively. There are eight sensors 15-1 to 15-1.
A reference visual field sensor having 5-8 photosensitive parts and on which a subject image pattern is formed through the optical system,
The sensor is constituted by a line image sensor using a charge storage type photoelectric conversion element such as a CCD. Also, there are 16 sensors 16 16-1 to 16-
The reference visual field sensor has 16 photosensitive parts, and the image pattern of the subject is imaged at a position according to the focusing state of the lens through the optical system, and the sensor is also composed of a line image sensor as described above. Ru.

Photosensitive parts 16-5 to 16-1 of the sensor 16
On the top of 2 is the photosensitive part 15- of the sensor 15 in the focused state.
The optical system is arranged so that the same image pattern as that imaged on 1-15-8 is imaged.

AD is clocked from sensors 15 and 16, which will be described later.
This is an AD converter that sequentially converts the charge (photoelectric conversion signal) accumulated in each photosensitive section, which is serially output in synchronization with CLK, into a sampling hold. Although this embodiment shows an example in which each charge is converted into a 2-bit digital value, it is also possible to convert it into a multi-bit digital value to improve accuracy.
It is of course possible to use an AD converter.

SR1 and SR2 are 8-bit and 16-bit shift registers, respectively.
2 are SR1-1, SR1-2, SR2-1, respectively.
It is composed of two columns of shift registers SR2-2, and inputs and stores the information AD-converted by the AD converter sequentially in synchronization with the clock.

The registers SR1-1 and SR2-1 constituting the registers SR1 and SR2 are storage registers for the first bit information of the AD-converted digital value, and the registers SR1-2 and SR2-2 are
forms a storage register for the second bit information of the digitel value.

C24 is a counter that latches and outputs a high level signal (referred to as a Hi signal) by counting 24 pulses of the clock CLK. The output of the counter is input to the AND gate A1 via the inverter I1, and with this configuration, the AND gate A
1 is 24 clock pulses directly or OR gate O1
The signal is transmitted to the clock input terminal CLK of the registers SR1 and SR2 through the register SR1 and SR2. By the way, register SR
1, SR2 sequentially inputs the digital values from the AD converter in synchronization with the clock pulses input through the AND gate A1, and shifts them to the right, and registers SR2 at the 24 clock pulses.
Digital values corresponding to the charges accumulated in the photosensitive parts 16-1 to 16-15 are stored in the first bit part B _- 1 to the 16th bit part B _-16 , respectively, and the first bit part _A- of the register SR1 is stored. Digital values corresponding to the charges accumulated in the photosensitive sections 15-1 to 15-8 are stored in the ₁ to 8th bit sections A _-8 , respectively.

CN1 and CN2 are 3-bit and 4-bit binary counters, respectively.
The clock input of is connected to the output of AND gate A2. The input terminal of the AND gate A2 is connected to the output terminal of the counter C24, and in response to the Hi signal from the counter C24, the AND gate A2 is opened and the counter CN1 is opened.
starts counting operation of clock CLK.

SEL1 and SEL2 are 8 line to 1 line data selectors, whose input terminals A, B, and C are connected to the output terminals A, B, and C of the counter CN1, and the sensors 15 and 1 are connected to the registers SR1 and SR2.
After the signals accumulated in 6 are transferred as described above, the selector SEL1 sequentially selects the first bit part of the register SR1 by the counting operation of the counter CN1.
The digital values stored in A _-1 to 8th bit part A _-8 are read out, and selector SEL2 sequentially reads out the 1st bit part B _-1 to 8th bit part of register SR2.
B Read out the digital values stored up to _-8 . The output terminal C of the counter CN1 above is the inverter I
2 and said register via OR gate O1.
It is connected to the clock input terminal of SR2, and the register SR2 performs a 1-bit right shift every time the signal from the output terminal C of the counter CN1 changes from the Hi signal to the low level signal (hereinafter referred to as the LO signal). . Therefore, the selector SEL1 selects the photosensitive sections 15-1 to 15- stored in the first bit section A _-1 to the eighth bit section A _-8 of the register SR1.
At the same time, the selector SEL2 sequentially outputs the contents of the first bit section B _-1 to the eighth bit section B _-8 of the register SR2 _. Each time the contents of ₁ to B _-8 are output, shift register SR2 is set to 1.
The bits are shifted and the output operations of the contents of B _-1 to _{B -8} are repeatedly executed. Therefore, the selector SEL
2 sequentially output digital values corresponding to the charges accumulated in the photosensitive sections 16-1 to 16-8,
Thereafter, digital values corresponding to the charges accumulated in the photosensitive sections 16-2 to 16-9 are outputted, and thereafter, the reading operation of the digital values is executed while shifting each photosensitive section one by one.

Now, the 1st bits A _-1 to 8th bits of register SR1
Bit part A Each digital value stored up to _-8
AC1 to AC8 (AC1 to AC8 are photosensitive parts 15-
It shows values corresponding to accumulated charges of 1 to 15-8. ), and the first bit part B _-1 of register SR2 ~
Each digital value stored up to the 16th bit part B _-16 is stored in BC1 to BC16 (BC1 to BC16 are the photosensitive part 1
This corresponds to the accumulated charges of 6-1 to 16-16. )
Then, with the above configuration, each digital value is output from the selectors SEL1 and SEL2 as shown in the table shown in FIG. (Register SR1, SR2 1st
A series of read operations from the bit part to the eighth bit part is called a sense. In this embodiment, the first to ninth senses are executed. ) CAL1 is an absolute value subtracter and the selector SEL above
The outputs from SEL1 and SEL2 are compared, and the smaller value is subtracted from the larger value to generate an output as shown in Figure 5.

SIG is an adder which sequentially adds the outputs from the subtracters and generates an addition output for each sense as shown in FIG.

As described above, the predetermined eight continuous photosensitive parts of the sensor 16 include the photosensitive parts 15-1 to 15-1 of the sensor 15.
Since the same image pattern as that imaged on 5-8 is imaged, the charge accumulated on the photosensitive part of the sensor 16 on which the same pattern as the imaged pattern of the sensor 15 is imaged is The above-mentioned addition output based on this will be approximately zero. That is, now sensor 16
Assuming that the same image pattern as the photosensitive parts 15-1 to 15-8 of the sensor 15 is formed on the photosensitive parts 16-1 to 16-8 of the register SR1 and SR
Since the digital values of the corresponding bit portions of 2 indicate the same value, the result of the above-mentioned subtraction and addition in the first sense is zero. Furthermore, if the same image pattern as that of the sensor 15 is formed on the photosensitive parts 16-2 to 16-9 of the sensor 16, the addition output of the second sense becomes zero, and the image pattern of the sensor 15 is similarly formed. The addition result obtained by sensing the photosensitive portion on the sensor 16 on which the same image pattern is formed becomes zero. Therefore, by detecting the sense number whose addition result is zero, the image formation position of the image pattern on the sensor 16 can be determined. Furthermore, as mentioned above, when focusing, the same pattern as the image pattern of the sensor 15 is formed on the photosensitive parts 16-5 to 16-12 of the sensor 16, so when focusing, zero is output at the fifth sense. Therefore, the difference between the sense number when the addition result becomes zero and the sense number (fifth) when in focus represents the amount of deviation from the in-focus state.

MIN detects the above output of adder SIG, detects zero (minimum value) among the above added values at each sense output from the adder, and generates output signal T when the minimum value is detected. and latches the signal T.
Configure the minimum value detector to send to LCH. The latch LCH is the output terminal D of the binary counter CN2.
-G are connected to the input terminals _D1 to _D4 , and in response to the output signal T, the output state of the counter CN2 is latched.

The counter CN2 has a clock terminal connected to the output terminal C of the counter CN1, and performs a counting operation in response to a signal change (from a Hi signal to a Lo signal) from the output terminal C of the counter CN1. Therefore, the output of the counter CN2 shows the output state shown in FIG. 5 every time each sense is completed. As mentioned above, the latch circuit latches the output of the counter CN2 in response to the signal T from the minimum value detector, so in the process of each sense, the output of the counter CN2 when zero (minimum value) is detected is Latched. Therefore, the digital value corresponding to the sense number when the adder reaches the minimum (zero) is held. As mentioned above, these registers are used when focusing.
A focus detection circuit is composed of SR1, SR2, selectors SEL1, SEL2, counter CN2, subtracter CAL1, adder SIG, minimum value detector MIN, and latch circuit LCH.

M is a motor as a driving means for driving the photographic lens and adjusting the distance based on the digital value latched in the latch circuit, and this motor is driven by a driving circuit consisting of transistors Tr ₁ to Tr ₄ . .

_I3 to _I6 are inverters, A3 is an AND gate,
OR2 to OR4 are OR gates, and these elements supply forward and reverse rotation signals for the motor M to the drive circuit based on digital values as distance information stored in the latch circuit LCH, and
A control circuit is formed to control the distance adjustment operation according to No. 2. Reference numeral 22 denotes a contact piece that moves in conjunction with the lens 12 and indicates a position corresponding to the position of the lens 12. 21 is a comb tooth-shaped brush contact that comes into contact with the contact piece 22;
The sliding of the contact piece 22 on the contact point 21 generates a pulse.

PD is a light receiving element provided near the sensor 15, which detects the average amount of light received by the sensor 15 and outputs an AGC signal.

CD is a drive circuit that generates drive pulses such as the clock CLK and controls the sequence of the entire device and the storage time of the sensor.

Although only a single selector SEL1 is shown in the figure, in reality, it is for register SR1-1, SR1
-2 are provided, SR1-1 and SR1-2.
The information of each bit of is output in parallel according to the input of counter CN1. Therefore, 2-bit digital values are sequentially output as information on the accumulated charge in each photosensitive portion of the sensor. Also, like selector SEL1, selector SEL2 is actually for SR2-1 and SR2-
There are 2 for 2.

FIG. 6 is a circuit diagram showing an embodiment of the drive circuit shown in FIG. 4. In the figure, CG is a pulse generator,
CN3 is a 3-bit counter, DEC is a 3-8 line decoder, and RM is PLA. At the timing shown in FIG. 7, drive pulses φ1, φ2, φR are applied to each sensor 15, 16 shown in the sensor section 20 in FIG. 4. (Here, the sensor is assumed to operate with a two-phase clock) to operate the sensor, output a sampling hold pulse S/H to the AD converter AD, and further output the clock CLK via the AND gate A12. Output.

The AD conversion time of the AD converter in Figure 4 is S/H.
It is assumed that the pulse ends at about twice the pulse. Therefore, after the above sensor outputs the output VOOT, S/
It is sampled with the H pulse and AD converted, and at the next rising edge of clock CLK, shift register SR1 is
can store digital information.

SW10 is a switch serving as a mode switching means that is connected to terminal O in natural light mode and to terminal U in auxiliary light mode.

T1 is the connection terminal for the auxiliary light strobe, and T1 indicates Hi when the strobe is fully charged.

PUS is a power-up clear circuit that outputs a pulse when the power is turned on, and the power-up clear circuit triggers a one-shot circuit ON1 via an OR gate O12. A10 and A11 are AND gates that constitute switching gates between natural light mode and auxiliary light mode.
SW10 is on the terminal U side) is the above AND gate A1
0 outputs Hi in response to the charging completion signal from terminal T1 and the pulse from one-shot circuit ON1,
AND gate A11 outputs Hi in response to the pulse of one-shot circuit ON1 in the natural light mode.

FF1 is a flip-flop (referred to as FF).
The FF is set in response to a Hi signal from the AND gate A10, sets the Q output to Hi, and transmits a strobe trigger signal to the terminal T3 to trigger the strobe. Hi of the above AND gate A11 and Hi of FF, FF1
is D type FF, FF2 D via OR gate O11
Applied to the input end. The output state of the FF2 is determined in accordance with a signal applied to the D input terminal in synchronization with the sensor drive pulse φ2. Therefore, with the above configuration, DFF and FF2 output Hi from the Q output when the power is turned on in the natural light mode, and Hi from the Q output when charging of the strobe is completed in the auxiliary light mode. FF4 is a FF that is reset by a pulse from the one-shot circuit ON1, and outputs Hi from the Q output when the power is turned on. A15 is the above FF, FF
4. An AND gate connected to the output of FF2,
When the Q output of FF2 becomes Hi, that is, the output becomes Lo as described above, the shift pulse φT becomes Lo and the sensors 15 and 16 start the charge accumulation operation.

A capacitor C is connected to the photodetector PD and constitutes an integrating circuit for charging the charge from the PD, and a transistor TR as an integration start switch is connected in parallel to the capacitor C. The transistor TR is connected to the output of FF2, is turned off by Lo of FF2, and the integration operation by the above-mentioned integration circuit is started. CP1
is a comparator circuit that compares the integrated output with the voltage level divided by resistors R1 and R3, and its output is the same as the above FF1.
connected to the reset terminal of the Yotsute FF1
sets the Q output at the output of the comparator circuit CP1 to Lo, and sets the output of the AND gate A15, that is, φT, to Hi to end the accumulation of the charges accumulated in the sensors 15 and 16. The integration circuit and comparison circuit constitute a timer circuit for controlling accumulation time. AS is above
An analog switch that turns on at the output of FF1.
The switch AS and the resistor R2 connect the resistor R2 to the resistor R3 and reduce the reference level for the comparator circuit CP1 when the switch is turned on.
constitutes an accumulation time adjustment means for reducing the reference level and shortening the accumulation time.

FIG. 8 is a circuit diagram showing an embodiment of the adder SIG and the minimum value detector MIN shown in FIG. 4.

The adder SIG has input terminals A1 and A2 connected to the output terminal of the subtracter CAL1 and an AND gate A20.
~Output Q1~Q of latch DLH1 via A23
an adder section with input terminals B1 to B4 connected to
I have ADD. The adder ADD adds the digital values to the A and B input terminals and generates the above-mentioned addition output at the output terminals X1 to X4. The output terminals X1 to X4 of the adder ADD are connected to the input terminal D1 of the latch DLH1.
~D4, the latch is connected to
Latch the output of the adder in synchronization with CLK. The input terminals of the AND gates A20 to A23 are connected to the output terminals A, B, and C of the counter CN1, and the count value of the counter CN1 is 0 to 0.
7, that is, while each of the above senses is executed, the latch output is connected to the input terminal B1 of the adder.
～Tell B4.

In the above configuration, the adder ADD adds the digital values output from the subtracter CAL1 while the AND gates A20 to A23 are open, that is, while the count value of the counter CN1 is 0 to 7, and Each time the sensing ends, the addition output shown in Figure 5 is
Output from SIG.

In the minimum value detection circuit MIN, DLH2 is a latch, and the outputs Q1 to Q4 of the latch are connected to the input terminal of the data selector SEL20. The output of the adder SIG is also input to the data selector, and the output of the adder or the latch circuit DLH2
selects the output of and transmits it to the latch circuit DLH2.
The latch circuit DLH2 is connected to the C of the counter CN1.
The input signal is latched every time the signal changes from Hi to Lo at the output terminal, that is, each of the first to ninth senses ends.

O22 is an OR gate connected to the outputs D to G of the counter CN2, and this gate outputs Lo until the first sense ends, and outputs Hi after the second sense. Hi of the OR gate O22 is input to the selector SEL20 via the OR gate O21. The or gate O21 is a selector
This is a gate that forms a selection signal Hi for selecting the output of the adder SIG input to SEL20 and transmitting it to the latch circuit.
2, the digital value accumulated and added by the adder SIG at the end of the first sense is latched.

A25 is an AND gate that outputs a selection signal Hi for selecting the output of the latch circuit DLH2 to be input to the selector SEL20 and returning it to the latch circuit DLH2.

COM is the output of the above adder and latch circuit DLH2
When the adder output value > latch circuit output value, Hi is output from a output, and when adder output value ≦ latch circuit output value, output b outputs Hi.
Output Hi. The comparator COM compares the accumulated addition value at the end of each sense with the contents of the latch circuit, and turns Hi from the OR gate O21 only when the output value of the adder ≦ the output value of the latch circuit. Output selector SEL20
The output of the adder is transmitted to the latch circuit, and the contents of the latch circuit are updated to the output value of the adder.
Therefore, the minimum value of the accumulated sum values obtained by the adder SIG is latched in the latch circuit for each of the first to ninth senses.

A26 is an AND gate, one input terminal of the gate is connected to the b output terminal of the comparator COM,
The other input end is connected to the OR gate O22. In this configuration, the AND gate A26 is the first
At the end of each sense after sensing, every time the b output of the comparator COM becomes Hi, the DFF outputs Hi.
Tell it to FF20. Therefore, DFF and FF20 are also comparators.
Every time Hi is output from COM, the output signal T is output, and as described above, the contents of the counter CN2 at that time are transmitted to the latch circuit LCH. Therefore, the latch circuit LCH latches the contents of the counter CN2 when the minimum added value is detected among the accumulated added values from the first to ninth senses.

FIG. 9 is a circuit diagram showing an embodiment of a strobe as an auxiliary light means applied to the focus detection device according to the present invention.

In the figure, 101 is a power supply, 102 is a power switch, and 103 is a booster circuit. The output of the booster circuit is charged to a main capacitor 105 via a rectifier diode 104. 106 and 107 are bleeder resistors that divide the charging voltage of the main capacitor, and 108 compares the output of the bleeder resistor with the reference voltage VRef, and when the charging level of the main capacitor exceeds a predetermined value, it outputs Hi as a charging completion signal. The output comparator 110 is an LED for indicating charging completion.

125 is an auxiliary discharge tube for generating the auxiliary light. 121 is a resistor, 123 is a capacitor,
124 is a transformer, and these circuit elements form the trigger circuit for the sub-discharge tube. 12
Reference numeral 2 denotes a thyristor which is turned on in response to the Hi signal from the terminal T3 in FIG.

126 is a main discharge tube for flash photography;
6 is triggered by a main light emission trigger circuit consisting of a resistor 115, a capacitor 117, and a transformer 118 to emit flash light. 116 is a thyristor for operating the trigger circuit for main light emission;
The thyristor is turned on by a normal synchro switch on signal of the camera inputted through the terminal T2, and operates the trigger circuit. 111
112 is an inverter, and 112 is a transistor. These circuit elements constitute a safety circuit that allows the thyristor 116 to be turned on only when the output of the comparator 108 becomes Hi.

127 is a thyristor connected in series to the discharge tubes 126 and 125;
5,126 is triggered and becomes ionized, it turns on and starts flashing light from the discharge tube.

133 and 129 are resistors, 130 is a capacitor, and 134 is a thyristor, which constitute a known commutation circuit for stopping the flashing of the discharge tube. The thyristor 134 has a diode 14
A Hi signal from the comparator CP1 shown in FIG. 6 is applied to the terminal T4 via the terminal T4, and in response to the Hi signal, the circuit turns on and performs a commutation operation. Further, the thyristor 134 has a diode 143 and a terminal T5.
Even when a light emission stop signal from a normal dimming circuit is applied through the main light emission and the amount of flash light emitted by the main light emission reaches a value that guarantees proper exposure, it is turned on and performs a commutation operation to stop the flash light.

139 is a capacitor, 140 and 141 are resistors, 138 is a diode, and 137 is a transistor. These circuit elements transfer the charge in the capacitor 139 to the discharge tube 125 or 12 when the flash is emitted.
6. Discharge through the thyristor 127, diode 138, and resistor 141, turn off the transistor 137 during this discharge time, and connect terminals T4 and T5.
This constitutes a safety circuit that allows the commutation circuit to respond to the light emission stop signal input to the device.

Next, the operation of the embodiment of the present invention shown in FIGS. 2 to 9 will be explained.

First, the auxiliary light mode will be explained.

In this mode, the switch SW shown in Figure 6
Connect 10 to terminal U. Assuming that charging of the strobe is now completed, Hi is applied to the terminal T1. When the camera's power switch (not shown) is turned on in this state, a power-up clear signal is output from the PUC, and the one-shot circuit is activated.
ON1 is activated and FF, FF2, and FF4 are reset as described above. Further, the pulse from the one-shot circuit sets FF1 via AND gate A10, and Hi is output from the Q output of FF1. The Hi
is connected to the thyristor 122 in FIG. 9 via the terminal T3.
is turned on, trigger circuits 123, 12
4 is activated, the discharge tube 125 generates a flash of light, illuminating the subject.

On the other hand, the Q output (Hi) of FF1 (Fig. 6) is transmitted to DFF and FF2 via OR gate O11.
The FF2 outputs Hi from the Q output and Lo from the output. Lo from the output of FF2 is AND gate A
15, the AND gate A15, which had been outputting Hi, synchronizes with the flash emission.
Output Lo. (In the initial state, FF4 and FF2 are reset when the one shot circuit ON1 is activated by the PUC, and A15 outputs Hi when the power is turned on.) The output of the AND gate A15 is the sensor shown in Figure 4. Acts as shift pulse φT of 15 and 16,
When the above φT becomes Lo, the sensor 15,
16 discloses the accumulation operation of the image pattern to be imaged. Also, at this time, the transistor TR (FIG. 6) is turned off by the output Lo of FF2, so that the capacitor C starts charging with the output current of the photodetector PD shown in FIG. 4.

Charging of capacitor C is started as described above, and the charging level is set to the reference level determined by resistors R ₂ , R ₃ , and R ₁ (analog switch AS is FF
It is turned on by the Q output (Hi) of No. 1, and the resistor R ₂ acts as the reference level determining factor. ), the comparator CP1 outputs Hi.

Hi from the CP1 is transmitted to the diode 142 in FIG. 9 via the terminal T4, and the thyristor 134
is turned on, the above-mentioned commutation circuit is activated, and the thyristor 127 is turned off using a known method, thereby stopping the flash emission by the discharge tube 125. Also, Hi from the comparator CP1 is transmitted to FF1 and resets FF1. For this reason, ORGATE O11 is also Lo
(Since A13 also outputs Lo when the signal from comparator CP1 is Hi, and AND gate A11 also outputs Lo, the inputs of OR gate O11 all become Lo when FF1 is reset.), and as a result, the output of FF2 but
Goes from Lo to Hi. Therefore, ANDGATE A15
returns the output φT to Hi as shown in φT b in Figure 7.
The charges accumulated in the sensors 15 and 16 are sent to an analog shift register within the sensor. Also, when FF2 becomes Hi, FF3 is clocked and the Q output becomes Hi, and the AND gate A1
2 is opened and the clock CLK (FIG. 7) is sent from the AND gate A12. When the clock CLK is sent from the AND gate A12, FF4 is set and its output is set to Lo, and the output φT of the AND gate A15 becomes Lo again as shown in FIG. blocked.

Through the above series of operations, the storage time control for the sensors 15 and 16 is executed, and the charges accumulated during the storage time are transferred to the registers in the sensors 15 and 16.

As mentioned above, the accumulation time of the image pattern by the sensor corresponds to the time for the integrated value of the photocurrent from the photodetector PD shown in Fig. 4 to reach the reference level, so regardless of the shooting brightness, the image pattern is accumulated by the sensor. The level of the image pattern signal (charge) is automatically amplified and adjusted to an appropriate level even when the image pattern has a low contrast, but when using fill light, the contrast of the subject itself increases. Therefore, there is no need to perform image signal level adjustment similar to the image level adjustment operation based on natural light. That is, as described above, since the image contrast itself increases when auxiliary light is used, the storage time may be shorter than when using natural light. Therefore, as described above, in the present invention, when using the auxiliary light, the reference level of the integrating circuit is lowered compared to the natural light mode, thereby eliminating the need for wasteful accumulation operation time and speeding up the AF operation. This also minimizes wasteful power consumption due to flash discharge.

As described above, when the image signal accumulation operation by the sensor is completed, the clock CLK is sent out as shown in FIG. like
It is converted into a digital value by an AD converter and transferred to shift registers SR1 and SR2. After this, the signals transferred to registers SR1 and SR2 are read out sequentially as described above, and the signals transferred to registers SR1 and SR2 are read out sequentially as described above.
Each sense up to the sense is executed. In addition, the above subtraction (Figure 5) and addition (Figure 5) are performed for each sense.
is executed. Then, among the addition outputs of the adder SIG in the first to ninth senses, the minimum value is detected by the minimum value detection circuit MIN as described above, and the output state of the counter CN2 at that time is detected by the latch circuit.
Latched to LCH.

As mentioned above, the content of the latch circuit LCH is a value representing the amount of deviation from the in-focus state, and in the in-focus state, the addition output at the fifth sense is the minimum, and the output of the counter CN2 at this time ( D=0 E=0 F=0 G=0) are latched in the latch circuit, so the lens is driven according to the amount of deviation and is automatically driven to the in-focus position.

That is, assuming that the front focus is currently on and an image of the same pattern as the sensor 15 is formed on the photosensitive parts 16-3 to 16-10 of the sensor 16,
Since the minimum value is detected as the addition output of the adder SIG in the third sense, the counter CN2 at that time
The outputs (D=0, E=1, F=0, G=0) are latched into the latch circuit. Therefore, the latch circuit
LCH outputs Q1 to Q4 (0, 1, 0,
0), the OR gate O2 outputs Lo indicating the front pin state, and the latch circuit enters the up-count mode. Further, the Lo from the OR gate O2 is converted to Hi via the inverter I3 and transmitted to the base of the transistor _Tr1 via the OR gate O4, so that _Tr1 is turned off and _Tr4 is also turned off. At this time, OR gate O3 outputs Lo (O2 outputs Lo, A3 also outputs Lo, and NAND gate N4 outputs Lo at the end of the ninth sense, so OR gate O3 outputs Lo.) Therefore, transistor Tr ₂ is turned on and therefore
Tr ₃ is also turned on. Therefore, the motor M rotates in the direction of arrow A and drives the lens 12 in a direction to shift from the front focus state to the rear focus state. When the lens moves in this manner, the brush contact 21 and the contact piece 22 slide due to the movement of the lens, generating a number of pulses corresponding to the amount of lens drive, and the latch circuit LCH
It is counted at As mentioned above, since the latch LCH is in the up mode, the pulses generated by the movement of the lens are counted, and when the latch circuit output becomes Q1 to Q4 = 0, 0, 1, 0 according to the counting result, the AND gate A3 outputs Hi, and the Hi is passed through the OR gates O3 and O4 to the transistors Tr ₁ ,
Transmit this to Tr ₃ , turn off Tr ₁ to Tr ₄ , and stop driving the lens.

Now, as mentioned above, the contents of the latch based on the sense result are Q1 to Q4 = 0, 1, 0, 0, so when the lens moves toward the pin after two pulses, the contents of the latch are Q1 to Q4 = 0, 0, 1, 0,
When the lens moves in the direction of the focus after two pulses, it moves to the in-focus position and completes the distance adjustment operation.

In this way, the lens is driven by the amount of deviation from the in-focus state latched by the latch circuit, and automatically shifts to the in-focus state. In case of rear pin, sensor 1 is attached to the photosensitive part after photosensitive part 16-6 of sensor 16.
Since the same pattern as 5 is imaged, the minimum value is detected after the 6th sense. Therefore, in this case, the contents of the counter are latched in the latch circuit while the output F or G of the counter CN2 is Hi, so Hi is output from the OR gate O2, and the latch circuit enters the down count mode and the transistor Tr ₁ and Tr ₄ are turned on, the motor rotates in the opposite direction from the front focus state, and the lens automatically shifts to the front focus direction by the amount of deviation from the focused state.

When the lens is in focus, the AND gate A3 outputs Hi as described above, and this Hi is applied as CNT4 to the AND gate A14 in FIG. 6, and the AND gate A14 outputs Hi. (After execution up to the 9th sense, NAND gate N4 in Figure 4
outputs Lo and Hi is applied to the other input of the gate A14 through the inverter I11, so the AND gate A14 outputs Lo because CNT4=Hi.
Output Hi. ) The one-shot circuit ON1 is triggered in response to the Hi signal from the gate A14. Therefore, after the lens is driven to the in-focus state, the accumulation operation and the lens driving operation by the sensor are repeatedly performed.

Next, the case of natural light mode will be explained.
In this case, switch SW10 in FIG. 6 is connected to the O side. Therefore, the AND gate A10 is held at Lo, and even if the PUC is activated by turning on the power, the FF1 remains in the reset state. Therefore, the strobe is prohibited from emitting light, and the analog switch AS is turned off, and the reference level is set to a normal level higher than that in the auxiliary light mode. Also, when the power is turned on, the one shot circuit turns ON1.
When activated, the AND gate A11 outputs Hi, and as a result of this Hi, the Q outputs of DFF and FF2 become Hi and the outputs Lo as described above, and the output φT of A15 becomes
The signal becomes Lo and the sensor starts the storage operation as described above, and when the charging voltage of the capacitor C by the output of the light receiving element PD reaches the reference level, the comparator CP1 outputs Hi. Therefore, in natural light mode, the sensor's accumulation time is regulated based on the normal reference level, and that level is automatically adjusted to the correct value, and from then on, the focus position by the lens is adjusted in the same way as in auxiliary light mode. The alignment is executed.

As described above, in the accumulation time control circuit for the focus detection device according to the present invention, the accumulation time is shortened when using the auxiliary light with the above configuration, so that the focus detection operation can be speeded up. This is something that can be done.

In the embodiment, the light receiving element PD is used to obtain luminance information for storage time control, but the luminance information may also be obtained using the sensor 15 or 16 itself. In this case, an image is stored in advance by a sensor for a certain period of time, the stored signal level is stored in a storage means such as a capacitor, and a current based on the stored value is generated by a transistor or the like.
The current may be used to charge the capacitor C in FIG. 6.

Further, although a strobe is shown as the auxiliary light source, it goes without saying that a spotlight (such as a normal lamp) may also be used as the light source. In this case, an FF is provided that is set in response to Hi from terminal T3 in Fig. 6, and when the FF is set, the switch that supplies power to the light is turned on, and in response to Hi from terminal T4. All you have to do is reset the above FF.

Further, as another example of the accumulation time adjustment means shown in FIG. 6, instead of providing the switch AS and the resistor R2, a
A transistor whose impedance decreases depending on the output (Hi) may be provided so that the capacitor is charged more rapidly when using auxiliary light than when using natural light. Also, as another example, switch AS and resistor R
2, a filter linked to the switch SW10 is installed in front of the light receiving element PD, and when it is natural light, light is irradiated to the light receiving element PD through the above filter, and when it is auxiliary light, the above filter is connected to the light receiving element.
It is also possible to remove it from the front of the PD so that the capacitor C is charged more quickly during supplementary light than when using natural light.

[Brief explanation of drawings]

Fig. 1 is a waveform diagram for explaining automatic gain control, Fig. 2 is a configuration diagram showing the configuration of a camera system to which the present invention is applied, and Fig. 3 is a configuration diagram showing the principle configuration of the focus detection optical system. , FIG. 4 is a circuit diagram showing an embodiment of a focus adjusting device to which the accumulation time control circuit according to the present invention is applied, FIG. 5 is an explanatory diagram for explaining the operation of FIG. 4, and FIG. 4 is a circuit diagram showing an embodiment of the drive circuit shown in FIG. 7. FIG. 7 is a waveform diagram explaining the operation of FIG. 6. FIG. 8 is a circuit diagram showing an embodiment of the adder and minimum value detector shown in FIG. 4. Circuit Diagram FIG. 9 is a circuit diagram showing one embodiment of a strobe as an auxiliary light source. PD...Photodetector, C...Condenser, CP1
... Comparison circuit, AS ... Analog switch, R2
……resistance.

Claims (1)

[Scope of Claims] 1. A light receiving sensor comprising a storage type photoelectric conversion element that receives a luminous flux from a subject and accumulates the received light signal, and a storage amount of the received light signal accumulated by the photoelectric conversion element to a predetermined amount. In an autofocus device that performs arithmetic processing for autofocus based on a light amount regulation circuit and the sensor output whose accumulation amount is regulated by the circuit, and performs an autofocus operation according to the calculation result, When the accumulation operation of the light reception signal by the photoelectric conversion element is performed without projecting the luminous flux from the light projecting means to the subject, the accumulation amount regulated by the light amount regulation circuit is set to a first value. a second value that is lower than the first value; and a second value that is lower than the first value; and a second value that is lower than the first value; An autofocus device characterized by having a setting circuit for setting.