JPH04191925A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To prevent the lowering of operation speed when an arithmetic result is zero by providing a holding means which is set when the arithmetic result of an arithmetic means is not zero, and hold a set state until the operation of all digits is completed and executing the zero discrimination of the arithmetic result by referring to the holding means. CONSTITUTION:When subtraction is executed materially by decimal addition/ subtraction arithmetic processing and moreover the result of it is zero, it is necessary to modify the code of the result into a positive code and when the arithmetic result by an arithmetic means 1 is any number except zero every time when an operation is executed by an arithmetic means 1, the effect of it is accumulate-held by a holding means 2. Then, the holding means 2 is referred to at the end of the operation of all digits and the holding means 2 is not set, that is, all the digits are zero, the code is modified into the positive code. Thus, the subtraction is executed materially by the decimal addition/ subtraction arithmetic processing and moreover even when the result of it is zero, the lowering of operation speed is prevented.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an arithmetic processing device that performs addition and subtraction operations on bank-format binary coded decimal numbers at high speed, and that performs subtraction in decimal addition and subtraction processing, and furthermore, performs subtraction in such a way that the result becomes zero. The purpose of the present invention is to provide an arithmetic processing device that can prevent the arithmetic speed from decreasing even in such cases, and includes an arithmetic means for performing addition and subtraction operations on decimal numbers of predetermined digits, and an arithmetic processing device in which the arithmetic result of the arithmetic means is not zero. The present invention is characterized in that it is provided with a holding means that is set at a time and holds the set state until the calculation of all digits is completed, and a zero determination of the calculation result is performed by referring to the holding means.

[Industrial application field]

The present invention is a bank-format binary coded decimal number (hereinafter simply "
The present invention relates to an arithmetic processing device that performs addition/subtraction operations on decimal numbers at high speed.

Generally, in electronic computers, programs for performing office processing are written in a language developed for office processing, such as COBOL.

In order for an information processing device to perform calculations and processing using such a language for business processing, the information processing device must have 10
It is necessary to handle decimal numbers.

One of the representation formats for decimal numbers handled by such electronic computers is the back format. The specifications of this puncture format decimal number will be explained below with reference to FIG.

■Each byte consists of the upper and lower 4 bytes except for the lowest 1 byte.
Both bits are called a numeric part, and are composed of any value from ``OM'' to ``9HJ'' (the subscript "-" does not indicate a hexadecimal number). If data other than 'ONJ-9H' is received in this numerical part, a data exception error will occur.

(4) The lower 4 vias of the rightmost byte (lowest byte) of the data are called the sign part, and for example, a positive number is expressed as "C8j" and a negative number is expressed as "D, l". Therefore, when data other than 'CMJ or 'DMJ comes into this code part, a data exception error occurs.

Note that the top four pinto points of the lowest hide are numeric parts.

Generally, such decimal numbers can be handled with variable length, and the length (number of digits) is specified as part of the instruction.

Therefore, when performing addition and subtraction operations using decimal numbers,
When handling data having a number of digits greater than the data width that the arithmetic processing device can operate on at one time, the operation for the designated digits is performed repeatedly.

By the way, according to the above decimal specification, when representing zero,
The number part is all "09", and the sign part is generally expressed as "C)IJ", that is, a positive number, and negative zero does not exist.

Therefore, if the operation result is all digits zero, it is necessary to make the sign part positive.

[Conventional technology]

Conventionally, addition and subtraction of decimal numbers has been realized by the process shown in the flowchart of FIG.

Basically, the signs of the summand and addend are checked, and if the signs are the same, addition is performed, and if they are different signs, subtraction is performed.

That is, first, it is checked whether the signs of the summand and the addend are both positive (step 531), and if both are positive, the resulting sign is set to be positive, that is, 'CMJ' (step 532).

On the other hand, if the signs of the summand and addend are both not positive, it is checked whether they are both negative (step 533), and if both are negative, the result sign is set to negative, that is, "DH". (
Step 534).

In the above two cases, the following additions are performed.

In this case, it is assumed that neither the summand nor the addend before the operation is negative zero (invalid data).

Once the sign of the result is determined as described above, the sign part is masked (set to zero) and addition is performed (step 535).
. Then, it is checked whether the calculation of all digits has been completed (step 536), and if it has not been completed, the next digit is taken out and 1
Perform 0-base addition and store the result (step 537);
Thereafter, steps S36 and S37 are repeatedly executed until it is determined that the calculations for all digits have been completed, and at the time it is determined that the calculations for all digits have been completed, the series of addition and subtraction processing of decimal numbers is completed.

On the other hand, if it is determined in step S33 that the signs of both the summand and the addend are not negative, it is checked whether the summand is positive and the addend is negative (step 338). and,
If it is determined that the summand is positive and the addend is negative, the sign of the result is set to positive (step 539), while step 5
When it is determined in 3B that the summand is positive and the addend is not negative, it is recognized that the summand is negative and the addend is positive, and the result sign is set to negative (step 540).

Thereafter, decimal subtraction processing will be performed.

That is, first, register a in which a predetermined register a is cleared to zero (step "54I") is a register for making a zero determination.

Next, the code part is masked, decimal subtraction is performed, and the result is stored (step 542). Then, the logical sum (indicated by the symbol ry) of the above subtraction result and the contents of the register is taken, and the result is stored in register a (step 54
3).

Then, it is checked whether the calculation of all digits has been completed (step 544), and if it has not been completed, the next digit is taken out, decimal subtraction is performed, and the result is stored (step 545).
. Next, the result of the subtraction is logically summed with the contents of the register, and the result is stored in register a (step 54).
6).

Thereafter, the above steps 544 to S46 are repeatedly executed until it is determined that the operation for all digits is completed, and at the time it is determined that the operation for all digits is completed, it is determined whether or not the subtraction result in the subtraction of the last digit is greater than or equal to zero. (Step 547). If it is determined that the value is greater than or equal to zero, it means that the subtraction has been completed without borrowing, so it is checked whether the contents of register a are zero (step 550), and it is determined that it is not zero. When this happens, the series of addition and subtraction processing of decimal numbers is completed.

On the other hand, if it is determined that the contents of register a are zero, the result sign is made positive (step 551). this is,
Since the sign of the result may have been assigned in advance in step S40, if the result of the operation is zero, this is done to correct it to a positive sign.

Further, if it is determined in step S47 that the result of subtraction of the last digit is smaller than zero, this means that the absolute value of the minuend is smaller than the absolute value of the subtrahend, so a complement calculation is performed (step 348). ).

This complement calculation is a process of taking the 10's complement of the result of the previous calculation, and is actually a process of subtracting the calculation result from decimal zero.

Then, the sign of the result is inverted (step 549), and the series of addition and subtraction processing of decimal numbers is completed.

[Problem to be solved by the invention]

In this way, in addition and subtraction processing of decimal numbers, since subtraction may actually be performed, the result may be all zero, and in this case, it is necessary to correct the sign part to make it positive.

Therefore, to check whether the result is zero, 1
It was necessary to accumulate the logical sum of intermediate results of decimal subtraction during decimal arithmetic processing. Therefore, a step of calculating a logical sum is required during the calculation loop, which has the disadvantage of reducing the calculation speed.

The present invention has been made in view of the above circumstances, and prevents the calculation speed from decreasing even when subtraction is actually performed in decimal addition/subtraction processing and the result is zero. The purpose is to provide an arithmetic processing device that can perform the following tasks.

[Means to solve the problem]

The arithmetic processing device of the present invention, as shown in principle in FIG.
Set when the calculation result of the calculation means 1 is not zero,
It is characterized by comprising a holding means 2 that holds the set state until the calculation of all digits is completed, and by referring to the holding means 2, the judgment of zero of the calculation result is performed.

[Effect]

If subtraction is actually performed in decimal addition/subtraction processing and the result is zero, it is necessary to correct the sign of the result to a positive sign. If the calculation result in is other than zero, that fact is cumulatively stored in the holding means 2, and when the calculation of all digits is completed, the holding means 2 is referred to, and if the holding means 2 is not set, the Therefore, if all digits are zero, the sign is modified to a plus sign.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the following explanation, 1 byte (1
A case will be described in which an operation is performed using a 2-digit 0-decimal number.

In the figure, 10 is a 1-byte X bus to which an addend or a minuend is supplied. 11 is 1 byte Y
bus, which supplies the addend or subtrahend.

The X bus 10 is connected to a selector 12, and a decimal check circuit (DCK) 13 and a +6 circuit (+6) 14 are also connected to the X bus 10. Similarly, the Y bus 11 is connected to the selector 15, and this Y bus 11 has a decimal number check circuit (DCK
) 16 and a complement circuit (CMP) 17 are connected.

The decimal number checking circuits 13 and 16 test the validity of the decimal number data, and check whether there is any invalid data other than "OH" to "9H" in the numeric part of the decimal number data.
It also checks whether there is invalid data other than the "CsJ, 'D) IJ base" in the code section, and if there is invalid data, it notifies the control section (not shown) to that effect. Normally, this is notified as a decimal data exception interrupt.

The +6 circuit 14 adds "
68'' is added and output. This +6 circuit 14
is used to check whether there has been a carry to the next digit as a lO base number by adding "6H" to the summand in advance and adding it to the addend.

The complement circuit 17 takes the two's complement of the contents of the Y bus 11, that is, the addend, and outputs it. Subtraction is made possible by adding the summand and the addend complemented by the complement circuit 17.

The selector 12 selects either the contents of the X bus 10 or the output of the
rALUJ) 1 is supplied to the X input.

Similarly, the selector 15 selects either the contents of the Y lotus 11 or the output of the complement circuit 17 and supplies it to the seven ALUIs.

ALIJI executes arithmetic operations or logical operations, and the operation results are output from the 0 terminal. Further, a carry signal generated during calculation is supplied to a carry bit holding circuit 19.

As mentioned above, the carry focus holding circuit 19 holds the carry signal generated by the calculation unit.
The microprogram is this carry focus holding circuit 19
By checking the contents of , it is possible to know whether there is a carry or not.

The output of the ALUI is supplied to the selector 20 and also to the -6 circuit (-6) 21.

The -6 circuit 21 is for adding "-6" to the output of the ALUI, and is used together with the +6 circuit 14 to perform correction during decimal calculation. That is, the above +6
As a result of adding the addend to the summand that has been increased by 6 in circuit 14, if a carry occurs, the result obtained is a correct decimal number, but if no carry occurs, the result is a decimal number that has been previously increased by 6j. Therefore, if the addition result is not r-6JL, it is correct 10.
I can't get a base number. This -6 circuit 21 is used to operate in such a case and obtain correct results.

The selector 20 selects whether to use the output of the ALUI as it is or to use the output of the -6 circuit 21 as the calculation result. The output of this selector 20 becomes the final calculation result.

A zero flag circuit (ZR) 22 is a flag that is set when the output of the selector 20, that is, the calculation result is zero, and changes every cycle. By checking the contents of this zero flag circuit 22, the microprogram is designed to be able to know whether or not the most recently executed operation is zero.

2 is an cumulative zero flag circuit (ADDINZ flag circuit) which is directly related to the features of the present invention.

The detailed configuration of this ADDINZ flag circuit 2 is shown in FIG.

That is, the ADDINZ flag circuit 2 operates as the OR gate 31 .
34, AND gates 32, 33, and a D type flip-flop 35 are connected as shown in the figure.

The output (8 bits) of the selector 20 is supplied to the OR gate 31. Therefore, selector 2
If even one bit of the 0 output is turned on, the output of the OR gate 31 is turned on. The output of this OR gate 31 passes through the 3B AND gate 32 and is supplied to the flip-flop 35 via the OR gate 34 if the addition signal supplied to the AND gate 32 is on. The addition signal provides the timing for zero determination, and is a signal that turns on at the timing when the calculation result is output from the selector 20. As a result, the flip-flop 35 is set unless the output of the OR gate 31 is on, that is, the calculation result of the ALU 1 is zero.

Once this flip-flop 35 is set, unless the reset signal becomes active (H level), the A
It is fed back through the ND gate 33 and the OR gate 34 to perform a self-holding operation.

Next, the operation of the above configuration will be described with reference to the flowchart of FIG. 4.

Basically, as in the past, the signs of the summand and addend are checked, and if the signs are the same, addition is performed, and if they are different signs, subtraction is performed.The processing details are shown in Figure 6. The processing is similar to that shown.

That is, first, it is checked whether the signs of the summand and the addend are both positive (step 5ll), and if both are positive, the resulting sign is set to be positive, that is, "C i J" (step 512).

On the other hand, if the signs of the summand and addend are both not positive, it is checked whether they are both negative (step 513), and if both are negative, the result sign is negative, that is, 'DMJ' (
Step 514).

In the above two cases, the following additions are performed.

In this case, it is assumed that neither the summand nor the addend before the operation is negative zero (invalid data).

Once the sign of the above result is determined, the sign part is masked (set to zero) and addition is performed (step 515). For this addition, first, the summand is placed on the X bus 10, and the addend is placed on the Y bus 10.
The signals are supplied to the bus 11 respectively. Then, the decimal number checking circuits 13 and 16 check whether the summand and the addend are correct decimal numbers. At this time, if it is determined that the decimal number is not correct, the following processing is stopped and the control unit is notified, for example, by an interrupt.

If both the summand and the addend are correct decimal numbers, the selector 12 supplies the output of the +6 circuit 14 to the X input of ALLII. That is, the value obtained by adding "6" to the summand becomes the summand. On the other hand, the selector 15 AL
Feed to Y input of UI.

Then, addition is performed in ALU1, and the result is output from the 0 terminal. At this time, if there is a carry, that fact is set in the carry bit circuit 19.

The data held in the carry bit circuit 19 is used as a selection signal for the selector 20.

That is, if the value of the carry focus circuit 19 is rl, the selector 20 selects the output of ALUI, and if it is r□, the output of the -6 circuit 21 is selected and output. The output of this selector 20 becomes the calculation result.

Flip-flop 3 inside ADDINZ flag circuit 2
5 is set if the operation result is not zero, and if it is zero, the original state is maintained. It is assumed that this flip-flop 35 has been cleared by a reset signal before starting the calculation.

Next, it is checked whether the operation of all digits given by the instruction has been completed (step 316), and if it has not been completed, the next one is
The bytes are extracted, decimal addition is performed, and the result is stored (step 517). This addition is also performed in the same manner as step 515 above. Thereafter, steps S16 and S17 are repeatedly executed until it is determined that the calculations for all digits have been completed, and at the time it is determined that the calculations for all digits have been completed, the series of addition and subtraction processing of decimal numbers is completed.

On the other hand, if it is determined in step S13 that the signs of both the summand and the addend are not negative, it is checked whether the summand is positive and the addend is negative (step 518); ,
If it is determined that the summand is positive and the addend is negative, the sign of the result is set to positive (step 519). On the other hand, step 3
When it is determined in 1B that the summand is positive and the addend is not negative, it is recognized that the summand is negative and the addend is positive, and the result sign is set to negative (step 520).

Thereafter, decimal subtraction processing will be performed.

That is, first, the ADDINZ flag is cleared (step 521). This ADDINZ flag is
This is the flip-flop 35 in the flag circuit 2, and is cleared when the reset signal goes to L level.

Next, the sign part is masked, decimal subtraction is performed, and the result is stored (step 522). For this subtraction,
First, the minuend is supplied to the X bus 10 and the subtrahend to the Y bus 11. And decimal check circuit 13.16
It is checked whether the minuend and the subtrahend are correct decimal numbers. At this time, if it is determined that the decimal number is not a correct decimal number, the following processing will be stopped and the control unit will be notified, for example, by an interrupt, in the same way as above.

If both the minuend and the subtrahend are valid decimal numbers, selector 12 supplies the output of X bus 10 to the X input of ALLII. On the other hand, the selector 15 selects the output of the complement circuit 17 as AL
Feed to Y input of UI. Then, addition is performed in ALUI, and the result is output from the 0 terminal. At this time, if there is a carry, that fact is set in the carry bit circuit 19. The data held in the carry bit circuit 19 is used as a selection signal for the selector 20. That is,
If the value of the carry bit 819 is "1", the selector 20 outputs the output of AL[Jl:J! Select the output of "16 circuit 2 if OΔ" and output it.

The output of this selector 20 becomes the calculation result.

Flip-flop 3 inside ADDINZ flag circuit 2
5 is set if the operation result is not zero, and if it is zero, the original state is maintained. It is assumed that this flip-flop block 35 has been cleared by a reset signal before starting the calculation.

Then, it is checked whether the calculations for all digits have been completed (step 523), and if not, the next l hide is taken out, decimal subtraction is performed, and the result is stored (step 523).
24). Thereafter, the above steps S23 and S24 are repeatedly executed until it is determined that the calculation of all digits is completed, and when it is determined that the calculation of all digits is completed, it is checked whether the subtraction result is greater than or equal to zero in the subtraction of the last digit. (Step 525). If it is determined that the value is greater than or equal to zero, it means that the subtraction has been completed without borrowing, so the 〇〇INZ flag is checked (step 328), and if it is determined that it is on, the sequence continues. The addition and subtraction processing of decimal numbers is completed.

On the other hand, if it is determined that the ADDINZ flag is zero, the result sign is made positive (step 529). This is because the result sign may have been made negative in advance in step S20, so the operation result is zero. In the case of , this is done to correct it to a plus sign.

Furthermore, if it is determined in step S25 that the result of subtraction of the last digit is smaller than zero, this means that the absolute value of the minuend is smaller than the absolute value of the subtrahend, so a complement calculation is performed (step 326).

This complement calculation is a process of taking the 10's complement of the result of the previous calculation, and is actually a process of subtracting the calculation result from decimal zero.

Then, the sign of the result is inverted (step 527), and the series of addition and subtraction processing of decimal numbers is completed.

In this way, since the zero determination of the calculation result is performed using the ADD fNZ flag circuit 2, the difference between FIG. 4 (step S23.524) and FIG. 6 (steps 344 to 5)
46), it is possible to omit the step of calculating the logical OR of the operation results for zero determination in the operation loop, and the addition and subtraction operations can be executed at high speed.

Note that in the above embodiment, a hardware configuration that performs an operation on one byte at a time has been described, but the hardware configuration is not limited to this, and may also be applied to hardware that performs an operation on 2 bytes, 4 bytes, or any other byte. The present invention can be similarly applied to a hardware configuration, and produces the same actions and effects as described above.

[Effects of the Invention] As detailed above, according to the present invention, even when subtraction is substantially performed in decimal addition/subtraction processing and the result is zero, the calculation speed decreases. It is possible to provide an arithmetic processing device that can prevent this.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 3 is a circuit diagram showing the configuration of an ADDINZ flag circuit according to the embodiment of the present invention. 5 is a flowchart showing the operation of the embodiment of the present invention, FIG. 5 is a diagram for explaining back format decimal numbers, and FIG. 6 is a flowchart showing the operation of conventional decimal addition and subtraction. 1...Arithmetic unit (ALU). 2... Holding means (ADDINZ flag circuit). In the figures, the same reference numerals indicate the same or corresponding parts. ! 45rJ'flrr)tPLll, IR Figure 1ADDINZ 7U7- Will 5Jt-n 4A
q Figure 3 Applicant: Fujitsu Co., Ltd., -1-f.
Agent Patent Attorney Sada Igeta -'---I゛4 Knee' Auto-light loss V Rino'#F8q to recite Figure 2 O, where Ij's movement r'p B-U- No. 4 Figure (1 of q)
2) Buff Length J1o Shimet (Fig. 5 Ktz) 1o Road Biting! Hesei's movement i Yfu σ - Figure 6 (T 1)

Claims (1)

[Scope of Claims] Arithmetic means (1) for performing addition and subtraction operations on decimal numbers of predetermined digits, and is set when the arithmetic result of the arithmetic means (1) is not zero, and the set state is reached when the arithmetic operations for all digits are completed. An arithmetic processing device, comprising: a holding means (2) for holding up to a maximum of 100, and determining whether a calculation result is zero by referring to the holding means (2).