JPH04192001A - Switch opening/closing action detector - Google Patents

Abstract

PURPOSE:To omit the need to use wirings in number more than the necessary switches and therefore to reduce the cost by judging the switch actions based on the logical levels given from a logical level holding means. CONSTITUTION:The diodes 14a and 14b are connected to a pair of switches 15a and 15b respectively in the directions opposite to each other. An inverter 3 is provided so that another logical level of the clock pulse given from a clock signal generator 1 emerges on a common signal line 18b when both switches 15a and 15b close independently of each other. Then the logical level signal emerged on the line 18b is held by a D flip-flop 9 for a period of time that is prescribed by the rise of the clock pulse signal received from a delay circuit 2. Thus the connection is secured for the switches 15a and 15b by means of three common signal lines 18a-18c less than the number of switches by one. Then no extra wiring is required.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention generally relates to a device for detecting open/close operation of a switch. It is equipped with a piston mechanism for automatically operating buttons and automatically transporting parts for supply, and includes a switch that is operated to close when the piston has the maximum stroke and when the piston has the minimum stroke. The present invention relates to a switch opening/closing operation detection device for detecting the opening/closing operation of a switch that is closed or a switch on an operation panel that is manually operated to start and stop an operation, change an operation procedure, etc.

(Prior Art) Generally, in an automatic assembly machine having the above-mentioned configuration, one of the means for detecting the operating status of the automatic assembly machine is
A switch is provided that is operated to close when the piston has a maximum stroke, and a switch that is operated to close when the piston has a minimum stroke. For example, microswitches are applied to both of these switches.

FIG. 4 is a diagram showing a conventional switch open/close operation detecting device provided to detect the open/close operation of such a microswitch. The conventional switch opening/closing operation detection device shown in FIG. 4 is provided to accurately grasp the operating status of the automatic assembly machine by detecting the closing operation of the microswitch. be.

The switch open/close operation detection device shown in FIG.
5a, 115b, inverter gates 117a, 117b
and a microcomputer 118.

The switches 113a and 113b are both normally open microswitches.
, 113b are both connected to a common line 122 which is grounded. The switch 113a also connects the connection line 1
21a. This connection line 121a includes the switch 113a, the pull-up resistor 115a,
Inverter game) 117a and microcomputer 1
It is connected to one input terminal 118a of 18. The switch 113b is also connected to the connection line 121b like the switch 113a.

This connection line 121b is connected not only to the switch 113b but also to the pull-up resistor 115b and the inverter gate 117.
b and the other input terminal 1 of the microcomputer 118
18b. Here, the switch 113a and the switch 113b are configured to close each other when one of the switches is at the maximum stroke of the piston and the other is at the minimum stroke of the piston. Pull-up resistors 115a, 115b
have the same resistance value. Connection line 121a.

121b and a pull-up resistor 115a, respectively.

The reason for connecting 115b is switch 113a.

When 113b is open, the microcomputer 1
Each of the 18 input terminals 118a and 118b has a logic level "
This is to ensure that a voltage signal of "L" is applied. In other words, when the switch 113a and the switch 113b, which are in the open state, are closed, a logic signal is applied to the input terminals 118a and 118b of the micro combinator 118, respectively. A voltage signal of level "H" will be applied.

The microcomputer 118 mentioned above is, for example, a microcomputer with a parallel processing bit count of 8 bits. This microcomputer 118 has eight data bars, and input circuits (
Reference numeral 1 is two of the eight input terminals (not shown).
18a and 118b are connected to an inverter gate 117a and an inverter gate 117b, and the microcomputer 118 is connected to a connecting line 121a and a connecting line 121.
It is configured to be able to read the logic level of b.

In addition, in FIG. 4, for convenience of illustration, the switch is designated by the reference numeral 1.
Although only two switches 13a and 113b are shown, up to eight switches can be connected even with the input circuit selected by one specific address, and by adding more input circuits, many switches can be connected. It is possible to connect. For example, even if an 8-bit microcomputer has eight data buses, if it has 16 address buses,
The maximum number of connectable switches is about 520,000.

(Problem to be solved by the invention) By the way, the switch 113a mentioned above.

113b, a common line 122 and two connection lines 121 corresponding to each switch 113a, 113b are provided.
a, 121b are required. That is, two switches 11
3a and 113b requires a total of three wires, two as connection lines and one as a common line. In this way, providing two switches requires three wires, including one common line, so for example, if eight switches are required, nine wires including one common line are required. This requires additional wiring, which may lead to higher costs.

If extra wiring is required compared to the number of switches to be installed as described above, a group of switches that must be installed close to the piston mechanism of the automatic assembly machine mentioned above,
If the distance between the microcomputer that receives logic level signals output from these switch groups and performs arithmetic processing operations becomes long, not only will this result in a significant increase in costs, but in some cases, the reliability of the equipment may be reduced. There was also the risk of problems such as a decline in performance and difficulty in maintaining the equipment.

Therefore, the present invention has been made in consideration of the above circumstances, and
The purpose is to provide a switch open/close operation detection device that can prevent high costs by creating a circuit configuration that does not require extra wiring than the number of switches that need to be installed. It's about doing.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention includes a set of a first switch and a second switch whose contacts are opened/closed by externally applied pressure or its release. In a switch opening/closing operation detection device that detects the opening/closing operation of at least one or more groups of switch edges for each switch, a square wave pulse signal that generates and outputs a square wave pulse signal of a predetermined logic level is used. A pulse signal generation/output means is provided in correspondence with the first switch of each set, and when the first switch of each set closes, the square wave pulse signal generation/output means outputs. a first semiconductor switching means that becomes conductive only when the square wave pulse signal is at one logic level; and a first semiconductor switching means that is provided in correspondence with the second switch of each group, and The second semiconductor switching means becomes conductive only when the other one of the square wave pulse signals outputted from the square wave pulse signal generation and output means is at the logic level due to the closing operation; is provided in correspondence with a first switch, and controls one logic level of the square wave pulse signal applied through the first semiconductor switching means after the first switch is closed. and a first logic level holding means that continues to hold the one logic level from the time when the first switch is opened to a time after the time when the first switch is opened; The other of the square wave pulse signals provided through the second semiconductor switching means is provided in correspondence with the second switch of each set, and after the second switch is closed, the other one of the square wave pulse signals is applied through the second semiconductor switching means. second logic level holding means that receives the logic level and continues to hold the one logic level from the time when the logic level is received until a time after the time when the second switch is in an open state; and when the one logic level is output from the first logic level holding means,
When it is determined that the first switch is in a closing operation and the one logic level is output from the second logic level holding means, it is determined that the second switch is in a closing operation. and determining means for determining that both switches are in an open state when the one logic level is not output from the two ring level holding means.

(Function) In the above configuration, when the first switch is caused to close due to externally applied pressure or release of externally applied pressure, a square wave pulse signal is generated and a square wave output from the output means is generated. One logic level of the wave pulse signal is applied to the first logic level holding means through the first semiconductor switching means. This one logic level is taken by the first logic level holding means after the time when the first switch is brought into a closed operation, and the time when the first switch is brought into an open state. The holding is continued by the first logic level holding means until a later point in time. While the first logic level holding means continues to hold the logic level, the one logic level is continuously outputted to the determination means. As a result, the means of judgment is
While it is determined that the first switch is in a closing operation, when the second switch is caused to close due to externally applied pressure or release of externally applied pressure, a square wave The other logic level of the square wave pulse signal output from the pulse signal generation and output means is applied to the second logic level holding means through the second semiconductor switching means.

One logic level generated by applying this other logic level to the second logic level holding means is such that the second switch is opened after the time when the second switch is caused to close. The second logic level holding means continues to hold the logic level until a point after the state has passed.

While the second logic level holding means continues to hold the logic level, the one logic level is continuously outputted to the determination means. As a result, the determining means determines that the second switch is in the closing operation.

Even if the timings of the closing operations of the first and second switches overlap, this causes the first and second logic level holding means to individually indicate the logic level of one of them to the determining means. Since the output is continuous, the judgment means
It is determined that both switches are closed.

1st. If both of the second switches are in the open state, the first and second logic level holding means do not output the logic level of one of them to the judgment means. It is determined that both are in the open state.

By having the above configuration, square wave pulse signal generation,
Alternatively, one common signal line may be used to connect the output means and the two switches, and between the first and second logic level holding means and the two switches, respectively. Since it is possible to determine which switch has closed based on the difference in the logic level of the signals, it is possible to create a circuit configuration that does not require more wiring than the number of switches that need to be installed, thereby reducing costs. It is now possible to prevent this from happening.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the overall circuit configuration of a switch opening/closing operation detection device according to an embodiment of the present invention.

The switch open/close operation detection device shown in FIG. 1 includes a clock signal generator (O8C) 1, a delay circuit 2, inverter gates 3, 6, 7, 8, and a current limiting resistor 4a.
, 4 bs switch section 5, D flip-flop 9,
10, 11, 12 and a microcomputer 13.

For example, the clock signal generator 1 has a frequency of 1 KHz,
Generates a clock pulse signal whose logic level "H" (represented by the symbol "vh") is approximately equal to the positive power supply voltage VCC and whose logic level "L" (represented by the symbol "Vl") is set to approximately 0. (See FIG. 3(A).) Then, this generated clock pulse signal is applied to the switch unit 5 through the common signal line 18a, and the signal line 19a
The signal is applied to the delay circuit 2 through the signal line 20a, and to the inverter gate 3 through the signal line 20a.

The inverter gate 3 has a common signal line 18a and a signal line 2.
After receiving a clock pulse signal from the clock signal generator 1 through 0a and inverting the logic level of the clock pulse signal, the current limiting resistor 4b is connected to the common signal line 18b through the current limiting resistor 4a. The signals are applied to the common signal line 18c through the respective signals. That is, when both the normally open switches 15a and 15b constituting the switch unit 5 are open, the clock pulse signal appearing on the common signal line 18b is opposite to the clock pulse signal appearing on the common signal line 18a. Become a phase. Similarly, the normally open switch 1 configuring the switch section 5 . When both channels 17a and 17b are open, the clock pulse signal appearing on the common signal line 18c is in opposite phase to the clock pulse signal appearing on the common signal line 18a.

The current limiting resistors 4a and 4b are connected to the normally open switch 1 described above.
This connection is made to prevent the inverter gate 3 from being short-circuited due to the closing operation of any one of 5a, 15b, 17a, and 17b. That is, the current limiting resistor 4a is provided on the signal line 20a, and connects the output side of the inverter gate 3 and the common signal line 18b. In addition, the current limiting resistor 4b is connected to the signal line 2.
0b, and connects the output side of the inverter gate 3 and the common signal line 18c. The current limiting resistor 4a uses an element with a fairly large resistance value. The reason for this is that while the normally open switch 15a is closed, the potential of the common signal line 18b becomes higher than the potential of the output side of the inverter gate 3, so a large current flows from the common signal line 18b side to the output of the inverter gate 3. This is to limit the flow to the sides. Similarly to the current limiting resistor 4a, an element with a fairly large resistance value is used for the current limiting resistor 4b. The reason for this is, as mentioned above, that while the normally open switch 17g is in the closing operation, the potential of the common signal line 18c becomes higher than the potential of the output side of the inverter gate 3, and a large current flows from the common signal line 18c side to the inverter. This is to limit the flow into the output side of the gate 3. Note that elements having the same resistance value are used for the current limiting resistors 4a and 4b. The signal waveform appearing on the common signal line 18b will be explained later with reference to FIG. 3(B). Since the contents are the same, the explanation will be omitted).

The delay circuit 2 receives a clock pulse signal output from the clock signal generator 1 through the common signal line 18a1 and the signal line 19,a. Then, as shown in FIG. 3(C), the received clock pulse signal is delayed by time t1 and output.

The clock pulse signal output from the delay circuit 2 is supplied to the clock pulse input terminal of the D flip-flop 9 through a signal line 19a, and to the clock pulse input terminal of the D flip-flop 11 through a signal line 19b. At the same time, the clock pulse signal output from the delay circuit 2 is applied to the inverter gate 7 through the signal line 19c, and its logic level is inverted by the inverter gate 7. The clock pulse signal whose logic level has been inverted by the inverter gate 7 is sent to the clock pulse input terminal of the D flip-flop 10 through a signal line 19d, and to the clock pulse input terminal of the D flip-flop 10 through a signal line 19e.
The clock pulse input terminals of the clock pulses are respectively supplied to the clock pulse input terminals of the clock pulse input terminals. The switch opening/closing operation detection device according to this embodiment includes:
The reason for providing the delay circuit 2 is that the common signal line 18
The clock pulse signal passing through the diode (14a.

14b, 16a, 16b), normally open switch (15a,
15b, 17a, 17b) and common signal lines 18b, 18
This is to avoid being affected by transmission delays caused by passing through c and waveform distortion caused by signal reflection. That is, following the above path, each D flip-flop 9
Each D flip-flop 9 to 12 starts holding the clock pulse signal after the time t1 when the clock pulse signal reaching the data input terminals 1 to 12 becomes stable.

As is clear from the above description, the switch section 5 includes diodes 14a, 14b, and 16a.

16b, and normally open switches 15a, 15b, 17a.

17b. That is, the series connection body of the diode 14a and the normally open switch 15a and the series connection body of the diode 14b and the normally open switch 15b are connected in parallel with each other with respect to the common signal line 18a1 and the common signal line 18b. . The above normally open switch 15a
and the normally open switch 15b form one set of switches. Similarly, the series connection body of the diode 16a and the normally open switch 17a and the series connection body of the diode 16b and the normally open switch 17b are connected to the common signal line 18a1 and the common signal line 18c.
are connected in parallel with each other. The normally open switch 17a and the normally open switch 17b form another set of switches.

Diode 14a is connected in the opposite direction to diode 4b. That is, the diode 14a has its anode terminal connected to the clock signal generator 1 side, and
Its cathode terminal is connected to the normally open switch 15a side. On the other hand, the diode 14b has its anode terminal connected to the normally open switch 15b side, and its cathode terminal connected to the clock signal generator 1 side.

Similarly to the above, the diode 16a is the diode 16b.
is connected in the opposite direction. That is, the diode 16a
has its anode terminal connected to the clock signal generator 1 side, and its cathode terminal connected to the normally open switch 17.
Connected to side a. On the other hand, the diode 16b has its anode terminal connected to the normally open switch 17b side, and its cathode terminal connected to the clock signal generator 1 side.

The normally open switches 15a, 15b, 17a, and 17b are, for example, microswitches or so-called panel switches that are manually closed. As is clear from the content already explained, the normally open switch 15a,
15b, 17a.

17b is for detecting the maximum stroke and minimum stroke of two piston mechanisms separately, or for detecting manual operation of an operation switch on an operation panel, for example, in an automatic assembly machine of a button telephone device, etc. It is set up for this purpose. In this embodiment, a normally open switch is used, but a normally closed switch may also be used.

In the diode 14a described above, when the normally open switch 15a is closed and the potential of the common signal line 18a is higher than that of the common signal line 18b, current flows through the diode 4a. That is, if the common signal line 18a is at the logic level "H", the potential at the output side of the inverter gate 3 is at the logic level "L", but since current flows through the diode 14a, the potential on the common signal line 18b increases. death,
A small current also flows through the current limiting resistor 4a. However, since the internal resistance of the diode 14a and the forward voltage drop of the diode 14a can be ignored, the logic level of the common signal line 18b becomes "H". On the other hand, when the logic level of the common signal line 18a is "L", the potential on the output side of the inverter gate 3 becomes the logic level "H", but the diode 14a is non-conductive because a voltage is applied in the opposite direction. Therefore, the potential of the common signal line 18b becomes logic level "H". That is, the logic level of the signal waveform appearing on the common signal line 18b when only the normally open switch 15a is closed is as follows.
Regardless of the logic level of the clock pulse signal output from the clock signal generator 1, the logic level is always “H”.
(See FIG. 3(B), signal waveforms from time T to time T2).

(2) When the normally open switch 15b closes the diode 14b, if the potential of the common signal line 18a is lower than that of the common signal line 18b, a current flows through the diode 14b. Therefore, for the same reason as explained in the section regarding the dionide 14a, when only the normally open switch 15b is closed, regardless of the logic level of the clock pulse signal output from the clock signal generator 1, both The communication line 18b is always at the logic level "L" (see the signal waveform from time T to time T4 in FIG. 3(b)).

Note that when the normally open switch 15a and the normally open switch 15b are closed at the same time, the diode 14a is conductive while the common signal line 18a is at the logic level "H", and the common signal line 18a is During the time when the logic level is "L", the diode 14b becomes conductive.Diode 1
Since the internal resistance and forward voltage drop of the diode 4a and the diode 14b are negligible, the clock signal output from the clock signal generator 1 to the common signal line 18a appears almost unchanged on the common signal line 18b. .

The D flip-flop 9 operates at the time when the first clock pulse signal outputted from the delay circuit 2 rises after the normally open switch 15a closes at time T1 in FIG. common signal line 1)
It begins holding the logic level "Hl" appearing on 8b.

The D flip-flop 9 maintains the logic level "H" at the time when the first clock pulse signal output from the delay circuit 2 rises (i.e., at time T3) after the normally open switch 15a becomes open at time T8. (refer to the signal waveform in Fig. 3 (D)).
. This operation of holding the logic level "H" by the D flip-flop 9 is carried out midway, that is, at time T2, when the normally open switch 15
Even if the logic level of the signal waveform on the common signal line 18b changes from "H" to "L" due to the closing operation of the common signal line 18b, the closing operation continues regardless of this. The reason for this is that during the period from time T to time T3, the common signal line 18b shown in FIG. 3(B) at the rising edge of the clock pulse signal shown in FIG. 3(C)
This is clear from the fact that the upper logic level is "H". The D flip-flop 9 outputs the signal shown in FIG. 3(D) to the microcomputer 13 through the signal line 21a.

The D flip-flop 10 operates at the time when the first clock pulse signal outputted from the delay circuit 2 through the inverter gate 7 rises (i.e., from time T2) after the normally open switch 15b closes at time T2 in FIG. When time t2 has elapsed: The clock pulse signal output from the inverter gate 7 appears on the common signal line 18b (as shown in FIG.
(The logic level of the signal waveform appearing on the common signal line 18b at this time is naturally "L2").The logic level "H" output by the D flip-flop 10 starts to be held. H'' is maintained at the time of the rise of the first clock pulse signal outputted from the delay circuit 2 through the inverter gate 7 after the normally open switch 15b is opened at time T4 (i.e., at time T4).
From time t'3. (3rd period has passed)
(See signal waveform in figure (F)). This D flip-flop 1
The operation of holding the logic level "H#" by 0 is not affected by the closing operation of the normally open switch 15a.

The reason for this is that during the period from time T to time T3,
This is clear from the fact that the logic level on the common signal line 18b shown in FIG. 3(B) at the rising edge of the clock pulse signal shown in ) is "L". The D flip-flop 10 outputs the signal shown in FIG. 3(F) to the microcomputer 13 through the signal line 21b.

Note that the diode 16 a that constitutes the switch section 5,
16 b s Normally open switches 17a, 17b, current limiting resistor 4b, common signal line 18C1, inverter gate 8, signal lines 19b, 19e.

20d and D flip-flops 11 and 12 will be omitted since they are the same as described above.

Since the maximum value of the aforementioned time delays t 1 , t', t 2 and t' is one cycle of the clock pulse signal, the normally open switches 15a, 15b, 17a.

When the opening/closing operation of 17b is fast, the clock signal generator 1 is adjusted so that the frequency of the clock pulse signal becomes high. In the above, the normally open switches 15a, 15b, 1
When there is chattering in 7a and 17b due to their opening/closing operations, it is preferable to adjust the clock signal generator 1 so that the frequency of the clock pulse signal is lowered. For example, if the chattering is 5 msec, the influence of the chattering can be eliminated by adjusting the frequency of the clock pulse signal to 100 Hz, that is, one period of the clock pulse signal to 10 msec.

In this embodiment, a microcomputer with a parallel processing bit count of 8 bits is used as the microcomputer 8, but a microcomputer with a parallel processing bit count of 4 bits or 16 bits may also be used.
The microcomputer according to the present invention is not limited to a microcomputer with a parallel processing bit count of 8 bits.

Furthermore, it is of course possible to use a programmable controller instead of the microcomputer.

As described above, according to one embodiment of the present invention, two switches 15a, 15b (or 17a) are provided.

17b) as one set, and diodes 14a, 14b (or 16a,
16b) is connected, and when one switch is closed and the other switch is closed, the clock pulse signal given from the clock signal generator 1 has a different logic level from the common signal line 18b ( 18c), and the logic level signal appearing on these common signal lines (or the logic level signal after the logic level has been inverted by the inverter gate 6.8) is outputted from the delay circuit 2 as a clock pulse. Since the time defined by the rising edge of the signal (or the rising edge of the clock pulse signal after the logic level is inverted by the inverter gate 7) is held in the D flip-flops 9 to 12, as in this embodiment, , when four switches are connected, there are three common signal lines (18a, 18b), one less than the number of switches.

18C), it became possible to connect these switches and reduce the number of signal lines connected.Also, it is possible to determine when the micro combi coater 13 reads data or when the switches are closed. Even if there is a slight delay, data can now be read accurately.

FIG. 2 is a diagram showing the overall circuit configuration of a switch open/close operation detection device according to another embodiment of the present invention. In the switch opening/closing operation detection device shown in Fig. 2,
Inverter gate 3 used in the device shown in FIG.
In place of the current limiting resistor 4a (or 4b), a current buffer amplifier 31, a first comparator 32, a second comparator 33, a reference voltage generation circuit 34, and a resistor 35 are provided. For convenience of illustration and explanation, only the diodes 14a + 14bs normally open switches 15a and 15b are shown in the switch section 5, and the same components as those shown in FIG. 1 are given the same reference numerals. Therefore, we have decided to omit their explanation.

In FIG. 2, the reference value voltage generating circuit 34 is constituted by a voltage dividing resistor connected between the positive power supply Vcc and ground. The reference value voltage generation circuit 34 includes a current buffer amplifier 3
The reference value voltage Vc is supplied to the first non-inverting input terminal through the signal line 37a.
For the inverting input terminal of the comparator 32, the signal line 3
A reference value voltage hrer is supplied through 6c. Similarly, the reference value voltage fr is applied to the non-inverting input terminal of the second comparator 33 through the signal line 36d.
et. Here, the reference value voltage Vc supplied from the reference value voltage generation circuit 34 to the current buffer amplifier 31 is set for example. Further, the reference value voltage href' supplied from the reference value voltage generation circuit 34 to the first comparator 32 is Vcc>
href, > V c l: Further, the reference value voltage Iref, supplied from the reference value voltage generation circuit 34 to the second comparator 33, is set to be V
It is assumed that the settings are such that C>Iref and >Ve.

The current buffer amplifier 31 has a voltage follower circuit configuration, receives the reference value voltage Vc applied from the reference value voltage generation circuit 34 through the signal line 37a, and transmits this reference value voltage Vc to the signal line 36a1 and the signal line 36a. The common signal line 18b and the signal line 3 are connected through the connected resistor 35.
6b, respectively. By supplying the reference value voltage Vc from the current buffer amplifier 31 to the common signal line 18b1 signal line 36b through the above path, when both normally open switches 15a and 15b of the switch unit 5 are in the open state, these signals are line 36a,
This means that the reference value voltage Vc is applied to 36b and 18b. Therefore, the interval in which only the normally open switch 15a transitions from the open state to the closed state ((Figure 3 (G) time T5
~ At time T6, each signal line 36a, 36b, 18b is
As shown in FIG. 3(G), a lock signal (that is, a clock signal whose logic level "H#" is the aforementioned "vh" and whose logic level "L-" is the aforementioned "Vc") is applied. Similarly, in the section in which only the normally open switch 15b is in the closed state (FIG. 3(G), from time T to time T8, each signal line 36a, 36b is closed).

18b, a lock signal (
That is, the logic level "H" is the logic level "H" at the "Vc".
The clock signal whose “L” is the “vl” is applied.

Furthermore, the above-mentioned normally open switch 15a1 normally open switch 15
b is in the closed state (Fig. 3 (G), time T
~ time T7), each signal line 36a, 36b, 18b
Then, the lock signal (i.e.,
The logic level "H" is the above-mentioned "vh" and the logic level "L"
” is applied with the clock signal “vIl#”.

The output side of the first comparator 32 and the D flip-flop 9
The output side of the second comparator 33 and the data input terminal side of the D flip-flop 10 are connected by a signal line 37c. There is.

The first comparator 32 determines the level of the reference voltage href' applied to the inverting input terminal from the reference voltage generating circuit 34 through the signal line 36c, and the level of the reference voltage href' applied to the non-inverting input terminal through the common signal line 18b. Compare the level of the signal waveform shown in (G). As a result of the above comparison, the level of the signal waveform shown in FIG. 3 (G) is the reference value voltage h
ref , the first comparator 32 outputs a voltage level signal of logic level "H" to the data input terminal of the D flip-flop 9 through the signal line 37b. Contrary to the above, Figure 3 (G)
The level of the signal waveform shown in is the reference value voltage href.

If it is determined that the level is lower than the level of , the first comparator 3
2 outputs a voltage level signal of logic level "L" to the data input terminal of the D flip-flop 9 through the signal line 37b (see the signal waveform in FIG. 3(H)).

The second comparator 33 compares the level of the reference voltage 1eef, which is applied from the reference voltage generation circuit 34 to the non-inverting input terminal through the signal line 36d, and the level of the reference voltage 1eef, which is applied to the inverting input terminal through the signal line 36b (FIG. 3). Compare the level of the signal waveform shown in G).

As a result of the above comparison, if it is determined that the level of the signal waveform shown in FIG. A voltage level signal of logic level "H" is output to the terminal. Contrary to the above, the level of the signal waveform shown in FIG. 3(G) is the reference value voltage 1ref.

If it is determined that the level is higher than the level of , the second comparator 3
3 outputs a voltage level signal of logic level "L" to the data input terminal of the D flip-flop 10 through the signal line 37c (see signal waveform in FIG. 3(1)).

As is already clear from the above content, normally open switch 1゛5
Even when the closing operations of both the normally open switch 15a and the normally open switch 15b overlap, the logic level comparison judgment by the first comparator 32 and the second comparator 33 is not affected by the difference.

The D flip-flop 9 receives a clock pulse signal (FIG. 3(C)) output from the delay circuit 2 through the signal line 19a.
(shown in FIG. 3(H)) and a logic level signal (shown in FIG. 3(H)) output from the first comparator 32 through the signal line 37b.

Then, as shown in FIG. 3(J), the logic level "H" signal continues to be maintained from time T'5 to time T'7. The logic level held by the D flip-flop 9 “
The H'' signal is applied to the microcomputer 13 through the signal line 21a.

Similarly, the D flip-flop 10 receives a clock pulse signal (shown in FIG. 3(E)) output from the delay circuit 2 and applied through the signal line 19d and the inverter gate 7.
and a logic level signal (shown in FIG. 3(1)) output from the second comparator 33 through the signal line 37c. Then, as shown in FIG. 3(K), time T
'6 to time T'8, the logic level "H" signal is maintained.The logic level "H" signal held by the D flip-flop 10 is applied to the microcomputer 13 through the signal line 2'lb. be done.

In the switch opening/closing operation detection device according to the other embodiment of the present invention described above, the voltage level of the signal lines 36a, 36b including the common signal line 18b varies from “vh” with reference to the voltage value “Vc”. It changes up to “Vρ”. Therefore, the first comparator 32 and the second comparator 33 are
Since only one power supply operation (0 to Vcc) is performed, it is also possible to use the same type of amplifier as the current buffer amplifier 31 for the first comparator 32 and the second comparator 33.

〔Effect of the invention〕

As explained above, according to the present invention, when the one logic level held by the first logic level holding means is output from the first logic level holding means, the first switch is closed. It was determined that the second
When the one logic level held by the logic level holding means is output from the second logic level holding means, it is determined that the second switch is in the closing operation, and the one logic level is output from the second logic level holding means. Since it is determined that both the switches are in an open state when the level is not output from both logic level holding means, the number of wiring required is one common signal line for half the number of switches used. By configuring the circuit in such a way that the number is the sum of

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the overall circuit configuration of a switch opening/closing operation detection device according to an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing the overall circuit configuration of a switch opening/closing operation detection device according to another embodiment of the present invention.
FIG. 4 is a timing chart showing the operation of each part shown in FIG. 1... Clock signal generator, 9.10.11.12... D flip-flop, 13
...Microcomputer, 14a, 14b, 16a, 16b-...Diode, 1
5a, 15b, 17a, 17b-=normally open switch, 31
...Current buffer 7 amplifier, 32...First comparator, 33...Second comparator, 34...Reference value voltage generation circuit. Applicant's agent Mr. Sato

Claims (1)

[Claims] 1. Opening/opening of at least one switch group including a first switch and a second switch whose contacts are opened/closed by externally applied pressure or its release; A switch opening/closing operation detection device that detects a closing operation of each switch separately includes a square wave pulse signal generation and output means for generating and outputting a square wave pulse signal of a predetermined logic level; When the first switch of each set is closed, one logic level of the square wave pulse signal output from the square wave pulse signal generation and output means is provided. a first semiconductor switching means that is in a conductive state; and a first semiconductor switching means that is provided in correspondence with the second switch of each of the sets, and when the second switch of each of the sets is closed, the square wave pulse signal is generated. , second semiconductor switching means that becomes conductive only when the other logic level of the square wave pulse signal outputted from the output means is provided; After the time when the switch is closed, it receives one logic level of the square wave pulse signal applied through the first semiconductor switching means, and from the time when the first switch receives the logic level of the square wave pulse signal applied through the first semiconductor switching means. a first logic level holding means that continues to hold the one logic level until a point after the open state, and a first logic level holding means that is provided in correspondence with the second switch of each set; After the time when the second switch is closed, it receives the other logic level of the square wave pulse signal applied through the second semiconductor switching means, and from the time of reception, the second a second logic level holding means that continues to hold the one logic level until a point after the time when the switch becomes open; and the one logic level is the first logic level. When the first logic level is output from the holding means, it is determined that the first switch is in the closing operation, and when the one logic level is output from the second logic level holding means, the first switch is determined to be closed. determining means for determining that the switch is in a closing operation and determining that both the switches are in an open state when the one logic level is not output from the both logic level holding means; A device for detecting open/close operation of a switch, characterized in that: 2. The switch opening/closing operation detection device according to claim 1, further comprising: receiving a square wave pulse signal outputted from the square wave pulse signal generation/output means, delaying the square wave pulse signal for a predetermined time, and outputting the square wave pulse. signal delay output means; first logic level inversion output means for inverting the logic level of the square wave pulse signal output from the square wave pulse signal delay output means and outputting it to the second logic level holding means; second logic level inversion output means for receiving the square wave pulse signal output from the square wave pulse signal generation and outputting means, inverting the logic level and outputting the inverted logic level; and from the second logic level inversion output means. One logic level determined by the output square wave pulse signal and the square wave pulse signal respectively output through each of the first and second switches when the switches are closed, and the other logic level. and third logic level inversion output means for inverting the level and outputting it to the second logic level holding means, and the square wave pulse signal generation and output means is configured such that the high logic level corresponds to a positive power supply voltage. a clock signal generator that generates and outputs a clock pulse signal set to an equal value and whose low logic level is set to approximately 0V, the first switch of each of the sets and the second switch of each of the sets; are connected in parallel between the clock signal generator, the first logic level holding means, and the third logic level inversion output means, and the second logic level inversion output means is connected in parallel with each other. , the first and second
The first semiconductor switching means is connected in parallel to the switch, and the first semiconductor switching means is configured to operate at a high logic level of the clock pulse signal output from the clock signal generator when the first switch closes. The second semiconductor switching means is a diode connected between the first switch and the clock signal generator so as to be in a conductive state, and the second semiconductor switching means a diode connected between the second switch and the clock signal generator so as to be conductive at a low logic level of the clock pulse signal output from the clock signal generator, and the first logic level The holding means sets one logic level of the clock pulse signal applied through the first switch to the first clock applied from the square wave pulse signal delay output means after the first switch is closed. From the rise or fall of the pulse signal,
D held until the rise or fall of the first clock pulse signal applied from the square wave pulse signal delay output means after the first switch becomes open.
The second logic level holding means is a flip-flop, and the second logic level holding means transfers one logic level of the clock pulse signal applied through the second switch and the third logic level inversion output means to the second switch. The second switch is activated from the rise or fall of the first clock pulse signal applied through the square wave pulse signal delay output means and the first logic level inversion output means after the closing operation is performed. The D flip-flop is held until the rise or fall of the first clock pulse signal applied through the square wave pulse signal delay output means and the first logic level inversion output means after it becomes an open state. A device for detecting open/close operation of a switch, characterized in that: 3. The switch opening/closing operation detection device according to claim 1, wherein the square wave pulse signal is output after receiving the square wave pulse signal output from the square wave pulse signal generation/output means and delayed by a predetermined time. signal delay output means; and logic level inversion output means for inverting the logic level of the square wave pulse signal output from the square wave pulse signal delay output means and outputting it to the second logic level holding means, The square wave pulse signal generation and output means is a clock signal generator that generates and outputs a clock pulse signal whose high logic level is set to a value substantially equal to the positive power supply voltage and whose low logic level is set to approximately 0V. The first switch of each set and the second switch of each set are connected to the clock signal generator, the first logic level holding means, and the second logic level holding means in parallel with each other. and the first semiconductor switching means is connected to a conductive state at a high logic level of the clock pulse signal output from the clock signal generator due to the closing operation of the first switch. The second semiconductor switching means is a diode connected between the first switch and the clock signal generator, and the second semiconductor switching means is a diode connected between the first switch and the clock signal generator. a diode connected between the second switch and the clock signal generator so as to be conductive at a low logic level of the clock pulse signal output from the generator, and the first logic level holding means The voltage level of the one logic level is determined only when the logic level signal given in response to the closing operation of the first and second switches is higher than a preset first reference voltage value. a first comparator circuit that outputs a signal; and a voltage level signal of the one logic level output from the first comparator circuit, which is connected to the square wave pulse signal after the first switch is closed. From the rising or falling time of the first clock pulse signal given from the delay output means, to the rise of the first clock pulse signal given from the square wave pulse signal delay output means after the first switch is in an open state. and a D flip-flop that holds the logic level signal until the falling edge of the switch. a second comparator circuit that outputs a voltage level signal of the one logic level only when the voltage level signal is lower than a second reference voltage value that is preset lower than the first reference voltage value; A voltage level signal of the one logic level output from the comparator circuit is applied through the square wave pulse signal delay output means and the logic level inversion output means after the second switch is closed. The first clock pulse signal is applied from the rise or fall of the first clock pulse signal through the square wave pulse signal delay output means and the logic level inversion output means after the second switch is in an open state. D to be held until the rise or fall of
1. A switch open/close operation detection device comprising a flip-flop.