JPH04192045A - Sequencer with rom type timer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a sequencer for measuring the order and timing of signal transmission between multiple pieces of hardware.

By using a ROM type timer, the hardware scale is less dependent on the WL complexity of the sequence that implements the sequencer, and the purpose is to make it easy to change the sequence. A necessary signal is sent to the hardware to start the first timer, and when a response signal is returned from the other hardware, after the first timer times out, a necessary signal is sent to the second timer and the first timer is started. If a response signal is not returned from other hardware before the timer times out, the sequencer receives the response signal as address information and outputs another required signal to start the third timer after the first timer times out. A ROM having the functions of a second timer and a third timer is provided by storing the output value of the counter indicating the timer and the pattern code corresponding to the desired timer operation.

[Industrial Application Field] The present invention relates to a sequencer for determining the order and timing of signal transmission between a plurality of pieces of hardware.

In recent years, there has been an increase in the number of operations in which signals are sent to multiple hardware functions by measuring their order and timing.
sequences) have been widely practiced.

In recent years, it has become possible to perform sophisticated responses on the signal receiving side, such as by installing a CPU on the hardware side that receives the signal. First, it has become extremely complex, as it requires receiving a response and determining the next sequence based on the result of that response. Therefore, as a timer serving as a reference time for generating these sequences, a timer is required that can flexibly combine a plurality of timers and select a plurality of patterns for the counter value depending on the state.

[Prior Art] Conventionally, for example, as shown in FIG.
A sequencer 3 is often provided to send signals and take timing between the computer and the hardware 2, and a certain sequence performed by this sequencer 3 will be described. Here, it is assumed that the timer required to realize this sequence is installed in the sequencer.

First, a sequence example in the case of normal termination will be explained using FIG. 3.

First, when the hardware 1 issues a start signal A to start a sequence, the sequencer 3 sends a signal A-1 to the hardware 2 and starts a first timer for confirming receipt of the response. Then, the sequencer 3 completes the first timer count.

Recognizing that the response to signal A-1 has been received from hardware 1, it further sends signal A-2 to hardware 1, starts a second timer, and monitors the reception of the response to signal A-2. .

When the sequencer 3 receives the response of the signal A-2 before the second timer finishes counting, the sequencer 3 sends the activation signal A response 1 to the hardware 1 and ends the sequence.

The above is a case in which all the assumed sequences end normally, but a sequence that should be handled as an abnormal state is shown in FIG. The example shown in FIG. 4 is a case where a response to signal A-1 cannot be received from hardware 2 for some reason. , and the response is monitored by another third timer. The result response returned to the hardware 1 also uses the activation signal A response 2 instead of the activation signal A response 1.

By the way, in the conventional technology, the above sequence function is realized using a random logic IC (gate circuit).

This is realized using flip-flops, counters, etc.), and the fifth
The figure shows how an example sequence can be implemented according to the prior art.

That is, this sequencer 3 includes a first timer counter 3o1 (hereinafter sometimes simply referred to as "first timer 301") and a second timer counter 302 (hereinafter sometimes simply referred to as "second timer 302"). , a third timer counter 303 (hereinafter sometimes simply referred to as "third timer 303"), integrating circuits 304 to 306 . Gate circuit 3
07 to 311, and in FIG.
At the same time, this starting signal A
is sent out as signal A-1.

Thereafter, after the first timer 301 finishes counting, the second timer 301 starts counting depending on the reception state of the signal A-1 response.
2. It is necessary to start one of the third timers 303, but this timer selection function is performed using the two AND gate circuits 30.
8,309 and one inverting gate circuit 307. The outputs of the two AND gate circuits 308, 309 are signals A-2. Corresponding to signal A-3, one of them is output, and in response, one of the timers is activated. Thereafter, if a response from the corresponding hardware 2 is received when the timer finishes counting, the AND gate circuits 310 and 311 send the specified activation signal A response (activation signal A response 1.activation signal A response 2) is returned.

[Problems to be Solved by the Invention] However, in such a conventional sequencer, random logic is assembled in order according to the realized sequence, and hardware is required for each operating point of the sequence. This means that the more complex the required sequence, the more hardware will be needed.

In addition, if there is a problem with the sequence that was considered at the design stage during equipment testing, or if the customer requests a change in the sequence, the only way to deal with this is to change the hardware. It is necessary to perform strap processing or pattern cutting processing on the board, or to change the printed board.

The present invention was made in view of such problems, and the RO
It is an object of the present invention to provide a sequencer with a ROM-type timer that uses an M-type timer so that the hardware scale is less dependent on the complexity of the sequence that implements the sequencer, and in which the sequence can be easily changed.

[Means for solving the problem] Therefore, the sequencer with a ROM type timer of the present invention has the following features:
When a piece of hardware issues a start signal, it sends the required signal to other hardware and starts the first timer,
When a response signal is returned from other hardware, the first
After the timer times out, the required signal is further activated and the second timer is activated.If a response signal is not returned from the other hardware before the first timer times out, the second timer is activated after the first timer times out. , a sequencer that performs at least the basic operations of issuing another required signal and starting a third timer, receives the response signal as address information, and stores the output value of the counter indicating the time and the pattern code corresponding to the desired timer operation. Accordingly, the present invention is characterized in that a ROM having the functions of a second timer and a third timer is provided.

[Function] In the above-mentioned sequencer with a ROM type timer of the present invention, when a certain piece of hardware issues a start signal, it sends a required signal to other hardware and the first timer is started, and the first timer is started, and the first timer is activated. When a response signal is returned, after the first timer times out, it further outputs the required signal and activates the second timer function of the ROM, while the response signal from other hardware is received before the first timer times out. If no response is returned, the basic operation of issuing another required signal and activating the third timer function of the ROM after the first timer times out can be performed.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
The sequencer 3 according to this embodiment shown in FIG. 1 includes a first timer counter 31 . Integrating circuit 32. It is configured with a ROM33.

Here, the first timer counter 31 is the hardware 1
It is triggered in response to the activation signal A from the first timer counter 301 of the conventional example. Then, this first timer counter 31 starts from '0HEXJ' to 'F'.
F) IEXJ is counted as one sequence, and this first timer counter 31 is
After counting up to J, it automatically becomes "0" and does not start counting until a new activation signal A is input.

The integrating circuit 32 receives the signal A-1 response, the signal A-2 response, and the signal A-3 response from the hardware 2 and outputs required address information to the ROM 33. That is, there are three signal reception states (signals A-1, A-
2. A-3 response), this signal is sent to the integrator circuit 32.
This is converted into a level signal and output as an address. Here, a 4-bit signal is output as the address to the ROM 33.

The ROM 33 receives signals based on the signal A-1 response, signal A-2 response, and signal A-3 response from the integrating circuit 32 as address information, and outputs a pattern corresponding to the output value of the counter indicating time and the desired timer operation. By storing the code, it has the functions of a second timer and a third timer.

Here, the second timer is a timer that is activated after the first timer counter 31 times out when a response signal is returned from the hardware 2, and corresponds to the second timer counter 302 in the conventional example. , the third timer is activated by the hardware 2 before the first timer counter 31 times out.
This is a timer that is activated when a response signal is not returned from the third timer counter 303 of the conventional example.

Now, if we compare this embodiment with the implementation example according to the prior art shown in FIG. In this embodiment, the selection circuit (AND gate circuits 308, 309, and inversion gate circuit 309) that switches the activation timer by the ROM 32 is replaced with the ROM 32. The reception status of signals A-1, A-2, A-3 and a count value for providing a time reference are input as address signals of this ROM 32, and all signals output from the sequencer to the outside are input to the ROM 32. It uses the output.

By the way, assuming the above circuit configuration, RO
The data written into M33 is shown in FIG.

Now, the operation will be confirmed below by associating FIG. 2 with FIGS. 3 and 4 showing the sequence. Note that the numbers in circles in each figure are the same in both figures.

(2): Upon reception of the activation signal A, the first timer counter (time reference timer) 31, which is the address of the ROM 33, starts and starts sending out the signal A-1 at the count r0001BxNJ. The signal A-1 continues to be output until rQ 100J (the count value of the first timer counter 31 at this time is 4), but this count value rQ
If the signal A-1 response is received at the time of 100J,
The ROM address jumps to (2), but if reception is not possible at this time, the operation continues to (2).

(2): When a signal A-1 response is received at count value ro 100J, after turning off all outputs for -1 time at ro 101J, signal A-2 is sent from rQ 110J to "10oo". At this time, the count value of the second timer is 3. Further, when the count value is "1000J" and the signal A-2 response is received, the process jumps to (2) in order to send the activation signal A response 1.

(2) Send activation signal A response 1 from count value rlooOJ to rllllOJ, turn off all output signals at rl 111J, and terminate the sequence.

■: This is a state inherited from the above ■ due to the non-reception of signal A-1 response, and all output signals are temporarily turned off at ro 101J.
After setting it to F, transmission of signal A-3 is started from ro 110J. This signal A-3 continues to be output until count rlO11J (the count value of the third timer is 6), but at the time of count value rlooIJ, the ROM address jumps to ■ by receiving the signal A-3 response. .

■From the second count value rlOOO,l to rllloJ,
The start signal A response 2 is sent, all output signals are turned OFF at rl 111J, and the sequence is terminated.

In this way, by writing the assumed sequence operation as data into the address of the state that can occur in the sequence, the same functions as were realized with conventional hardware can be realized with ROM33. It can be done.

The count input value that gives the code and time of the state that may occur in this way is input as an address to the ROM 33, and the R
By storing output patterns for all cases that occur in the sequence to be realized in the OM 33, it is possible to eliminate the need for timers and selection circuits specific to individual events in the sequence. Furthermore, the sequence can be easily changed by changing the burn-in pattern of the ROM 33.

In this way, functions similar to those conventionally realized in hardware can be realized only with the ROM 33 and the counter 31 for the first timer as a time reference counter, which allows for example Even if the sequence to be realized becomes more complex, such as by adding signals to the hardware 2, as long as the address space and output lines of the ROM 33 remain, the ROM 33
This can be done by simply changing the data, and there is no need to add hardware such as a timer as in the conventional technology.

This means that communication equipment that achieves an advanced duplex redundant configuration can flexibly respond to the complexity of coordination processing related to duplex switching operations, and as a result, the development of duplex equipment can be This makes it very easy.

[Effects of the Invention] As detailed above, according to the ROM-type timer-equipped sequencer of the present invention, even if the sequence for realizing the sequencer becomes complicated by using the ROM-type timer,
It is sufficient to simply write data to the ROM, and furthermore, to change the sequence, it is sufficient to simply change the data to the ROM, so there is an advantage that the sequence can be easily changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a diagram explaining a ROM pattern. FIG. 3 is a sequence diagram illustrating a sequence example at normal termination, and FIG. 4 is a sequence diagram illustrating a sequence example at abnormal termination. FIG. 5 is a block diagram showing a conventional example, and FIG. 6 is a block diagram explaining the connection relationship between hardware and a sequencer. In the figure, 1.2 is the hardware, and □ 3 is the sequencer. 31 is a counter for the first timer; 32 is an integrating circuit; 33 is a ROM; 301 is a counter for the first timer; 302 is a counter for the second timer; 303 is a counter for the third timer; 304-306 are integrating circuits; 307- 311 is a gate circuit.

Claims (1)

[Claims] When a certain hardware (1) issues a start signal, it sends a necessary signal to another hardware (2), starts the first timer (31), and starts the first timer (31). ), after the first timer (31) times out, it further issues the required signal and starts the second timer, while before the first timer (31) times out, the other If a response signal is not returned from the hardware (2), the sequencer performs at least the basic operation of issuing another required signal and activating the third timer after the first timer (31) times out. The ROM (33) having the functions of the second timer and the third timer receives the response signal as address information and stores the output value of the counter indicating the time and the pattern code corresponding to the desired timer operation. A sequencer with a ROM type timer.