JPH04192543A - Programmable logic device - Google Patents

Abstract

PURPOSE:To reduce the length of wiring and cut down the number of switch stations. CONSTITUTION:A switch station 13 is connected vertically and horizontally by wiring groups. In addition, the station is also connected by slanting wirings 17, 17a, and 17b which cross from two directions. This programmable wiring is designed to have a slanting wiring element in addition to vertical and horizontal directions. It is capable of reducing the length of wiring which connects programmable logic elements 11 relatively spaced apart from one another by a slanting wiring portion. It is also possible to reduce at least one switch station out of the stations which pass by.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to programmable wiring, a switch station that selectively connects the routes of these wiring, and a programmable wiring that is connected via an input/output switch array. Regarding a programmable logic device that has logic elements and realizes a desired functional element by arbitrarily programming these by a user,
In particular, programmable logic that improves the efficiency of wiring routed through each switch station.
It's about devices.

<Prior Art> A programmable logic device (hereinafter referred to as rPLDJ) has been known which has an internal structure in which logic can be programmed as a type of data.

Such a PLD includes a programmable logic element (hereinafter referred to as rPLEJ) consisting of, for example, one combinational logic circuit and two flip-flops, programmable wiring, a switch station that connects and disconnects these wirings, and an input/output switch array of the PLE. can be arbitrarily connected to enable a desired logic element.

The general configuration of such a PLD is as shown in FIG.
PLElol arranged in a matrix and these PLElol
Wiring lines 105 are arranged horizontally and vertically in a grid pattern between the LEs, and a switch station 1 is installed at the intersection of these lines.
03 is placed. Also, PLEIOI and wiring 1
05 is provided. Such switch station 103 is programmable so that only the desired wires are connected to PLElol.

When assembling a desired functional circuit by arbitrarily programming and wiring such PLEs 101, most of the PLEs 101
connects adjacent ones to form one logic-like block, but the remaining PLElol is designed to connect adjacent PLEIO blocks.
There are many cases where it is not possible to wire I to the shortest switch station 103. In such a case, the distributed PLEs are bypassed by the used wires and switch stations and connected to each other using unused wires and switch stations.
So-called detour wiring is used (see the wiring indicated by the thick line in FIG. 5). This is done in order to effectively utilize unused PLEs, and is a general method used to increase the efficiency of PLD usage.

<Problem to be solved by the invention> However, as mentioned above, performing detour wiring to connect distributed PLEs not only increases the length of the wiring connecting the PLEs, but also causes the wiring to be arranged vertically and horizontally. The number of lines passing through the switch station 103 that selects the line 105 will inevitably increase, which means that there will be a large delay in signal transmission between the PLEs connected by the line, and this delay will increase the operating speed of the PLD. This is undesirable because it causes deterioration.

An object of the present invention is to eliminate the undesirable points of the conventional PLD programmable wiring, and to reduce the length of wiring connecting switch stations, especially when detour wiring is required.
It is an object of the present invention to provide a programmable logic device which can be made shorter than the conventional one and which can also reduce the number of switch stations through which wiring connecting PLEs passes.

Means for Solving the Problems> In order to solve the above problems, according to the present invention, in a programmable logic device having programmable wiring that connects programmable logic elements in a programmable manner via a switch station, The present invention provides a programmable logic device characterized in that the programmable wiring has diagonal wiring elements in addition to vertical and horizontal wiring connecting each switch station.

<Operation of the Invention> According to the programmable wiring of the present invention, when the programmable wiring connected to the PLE connects switch stations arranged in a matrix, for example, it can have diagonal wiring elements in addition to the vertical and horizontal directions. By letting
The wiring length when connecting PLEs arranged relatively far apart can be shortened by the diagonal wiring, and
The number of switch stations traversed can also be reduced by at least one. In addition, by providing diagonal wiring in addition to vertical and horizontal wiring, the degree of freedom in wiring for the user is improved, making it easier to design detour wiring, etc., and reducing the reduction in signal transmission speed and signal attenuation. .

Therefore, since the wiring length and the number of switch stations are reduced, it is possible to realize a PLD that is excellent in terms of both high speed such as signal delay and reliability such as signal attenuation.

Note that diagonal wiring in programmable wiring refers to diagonal wiring in terms of architecture, and includes not only physical diagonal wiring but also what can be considered as diagonal wiring in a higher-level architecture.

<Embodiments> Preferred embodiments of the present invention will be specifically described below with reference to the drawings.

In this embodiment, first, the physical configuration of the PLD will be described. PLEs are arranged in a matrix on a chip, and three wiring layers, such as aluminum or polysilicon, are formed on the chip, and an insulating layer is formed on the chip. The PLEs are stacked through the PLEs, and wiring groups are extended to connect the PLEs vertically and horizontally in a three-dimensional manner. Switch stations as inter-wire switches for selectively connecting wires are also arranged on the chip, and wiring layers are connected to these switch stations. Typically, a switch station is comprised of a transfer gate, ie, a pass transistor, a switching means with memory, and the like.

FIG. 1 shows an architectural example of programmable wiring in which diagonal wiring is provided for the wiring connecting these switch stations. In addition to being connected vertically and horizontally by wiring groups, the switch stations 13 are
They are connected by diagonal wiring 17; 17a, 17b crossing from two directions. By the way, PLEII is selectively connected to the wiring 15 via an input/output switch array (not shown). In this figure, as mentioned above, the distribution! 1
3 is performed three-dimensionally, but for convenience, the state of the diagonal wiring is expressed two-dimensionally.

The diagonal wiring 17 may be provided on the same plane as the vertical and horizontal wiring, or only the diagonal wiring may be separated from the others and provided on another plane. Further, the diagonal wiring 17 may be provided in the entire wiring layer or only in a desired portion.

Figure 2 shows a modification of diagonal wiring, and shows a diagonal wiring in one direction!
Only 117-b (or 17a) is double wired. FIG. 3 shows physical wiring that is architecturally equivalent to the diagonal wiring shown in FIG. Diagonal wiring is also achieved by providing [17b] which does not pass through the switch station 13 in this way. In this case, although it is not expected that the wiring length will be reduced much, the number of wires passing through the switch station 13 can certainly be reduced. FIG. 4 shows another modification of FIG. 1, which is particularly effective when the PLEs are arranged relatively far apart, saves the number of passes through the switch station 13 and the length of the wiring, and further reduces the wiring. The degree of freedom is also increasing.

As described above, the method of physically realizing the programmable wiring shown in FIGS. 1 to 4 is not particularly limited, and various methods can be used as necessary. In addition, although several examples of diagonal wiring have been shown, various other examples of diagonal wiring can be considered, but increasing the number of wirings complicates the signal path, which may lead to various signal noises. Therefore, it seems that it is permissible to a certain extent.

Note that in the above embodiments, the programmable circuit elements arranged on the chip are not limited to PLE, but may be various elements or arbitrary circuits without changing the effects of the present invention. As described above, within the scope of the idea of the present invention, the present invention can be applied in various ways according to the spirit thereof, and can be implemented in various ways.

<Effects of the Invention> As is clear from the above description, according to the programmable logic device of the present invention, programmable wiring connected to a programmable logic element (PLE) can be connected to a switch stage arranged in a matrix, for example. By having diagonal wiring elements in addition to the vertical and horizontal directions, when connecting PLEs placed relatively far apart, or when detour wiring is required, the wiring length can be adjusted diagonally. The length of the wiring can be shortened and the number of switch stations to be passed through can be reduced by at least one. Further, by providing diagonal wiring in addition to vertical and horizontal wiring, the user's degree of freedom in wiring is improved, detour wiring, etc. can be designed easily, and deterioration in signal transmission speed and signal attenuation can be reduced.

Therefore, since the wiring length and the number of switch stations are reduced, it is possible to realize a programmable logic device (PLD) with good performance in terms of both high speed such as signal delay and reliability such as signal attenuation. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a schematic circuit layout diagram showing programmable wiring of a programmable logic device according to an embodiment of the present invention. FIG. 2 is a schematic circuit layout diagram showing similar programmable wiring illustrating another embodiment of the invention. FIG. 3 is a schematic circuit layout diagram showing a programmable wiring having the same architectural aspect as FIG. 2. FIG. FIG. 4 is a schematic circuit layout diagram showing similar programmable wiring illustrating another embodiment of the invention. FIG. 5 is a schematic circuit layout diagram showing programmable wiring of a conventional programmable logic device. Explanation of symbols 11... Programmable logic element, 13... Switch station, 15... Programmable wiring, 17... Diagonal wiring FIG, 1 7b FIG, 2 FIG, 3

Claims (1)

[Claims] (1) In a programmable logic device having programmable wiring that programmably connects programmable logic elements via switch stations, the programmable wiring has wiring connecting each switch station in a vertical and horizontal direction. In addition, a programmable logic device characterized by having a diagonal wiring element.