JPH04192902A - Hybrid integrated circuit device for high frequency - Google Patents
Hybrid integrated circuit device for high frequencyInfo
- Publication number
- JPH04192902A JPH04192902A JP2327749A JP32774990A JPH04192902A JP H04192902 A JPH04192902 A JP H04192902A JP 2327749 A JP2327749 A JP 2327749A JP 32774990 A JP32774990 A JP 32774990A JP H04192902 A JPH04192902 A JP H04192902A
- Authority
- JP
- Japan
- Prior art keywords
- film
- high frequency
- conductor
- signal conductor
- dielectric substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 230000010355 oscillation Effects 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000002265 prevention Effects 0.000 claims description 14
- 230000002238 attenuated effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004132 cross linking Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
Landscapes
- Waveguide Connection Structure (AREA)
- Non-Reversible Transmitting Devices (AREA)
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は高周波用混成集積回路装置に関し、特にその発
振防止回路の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high frequency hybrid integrated circuit device, and particularly to the structure of its oscillation prevention circuit.
［従来の技術］
第４図および第５図はそれぞれ従来の高周波用混成集積
回路装置の発振防止回路の断面構造図を示す。前者は発
振径路の信号導体膜ｌの一部を分離して帰還量減衰用の
下地抵抗膜２を中間に挿入した構造のものであり、また
、後者は同じく一部を分離した信号導体膜１の間に帰還
量減衰用のチップ抵抗２′を導体線または導体テープな
どの接続導体５で接続した構造のものである。ここで、
３および４は誘電体基板および接地導体を、また、１′
および３′は信号導体膜片およびチップ抵抗搭載用の誘
電体基板をそれぞれ示す。[Prior Art] FIGS. 4 and 5 each show a cross-sectional structural diagram of an oscillation prevention circuit of a conventional high-frequency hybrid integrated circuit device. The former has a structure in which a part of the signal conductor film 1 of the oscillation path is separated and a base resistive film 2 for attenuating the amount of feedback is inserted in the middle, and the latter has a structure in which a part of the signal conductor film 1 in the oscillation path is separated. In this structure, a chip resistor 2' for attenuating the amount of feedback is connected between them by a connecting conductor 5 such as a conductor wire or a conductor tape. here,
3 and 4 are the dielectric substrate and ground conductor, and 1'
and 3' indicate a signal conductor film piece and a dielectric substrate for mounting a chip resistor, respectively.
［発明が解決しようとする課題］
しかしながら、上述した従来の・高周波用混成集積回路
装置は、高周波信号線を直流バイアス供給線として共用
する場合が多く、抵抗膜にも高周波成分の外に直流バイ
アス電流が常時流れている場合が多い。従って、この構
造の発振防止回路は目的とする高周波成分の減衰のみで
なく、直流バイアスも低下させるという欠点な有する。[Problems to be Solved by the Invention] However, in the conventional high-frequency hybrid integrated circuit device described above, the high-frequency signal line is often used as a DC bias supply line, and the resistive film also has a DC bias supply line in addition to the high-frequency component. In many cases, current is constantly flowing. Therefore, the oscillation prevention circuit having this structure has the disadvantage that it not only attenuates the target high frequency component but also lowers the DC bias.
本発明の目的は、上記の情況に鑑み、直流バイアスを低
下させる往来発振防止用回路の欠点を解決した高周波用
混成集積回路装置を提供することである。SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a high-frequency hybrid integrated circuit device that solves the drawbacks of the circuit for preventing oscillation that reduces DC bias.
［課題を解決するための手段〕
本発明によれば、高周波用混成集積回路装置は、誘電体
基板と、前記誘電体基板の一主面に形成される信号導体
膜と、該信号導体膜と高周波信号線路を構成する前記誘
電体基板裏面上の接地導体とを含み、前記高周波信号線
路の発振径路には前記信号導体の一部切除領域と、前記
信号導体の一部切除領域上に露出する下地抵抗膜と、前
記信号導体の一部切除領域上の互いに離間する２つの信
号導体間を端部中央部で接続する前記下地抵抗膜のバイ
パス導電路とからなる発振防止回路が形成されることを
備えて構成される。[Means for Solving the Problems] According to the present invention, a high frequency hybrid integrated circuit device includes a dielectric substrate, a signal conductor film formed on one main surface of the dielectric substrate, and a signal conductor film formed on one main surface of the dielectric substrate. a ground conductor on the back surface of the dielectric substrate constituting a high-frequency signal line; the oscillation path of the high-frequency signal line includes a partially removed area of the signal conductor; and a ground conductor exposed on the partially removed area of the signal conductor. An oscillation prevention circuit is formed that includes a base resistive film and a bypass conductive path of the base resistive film that connects two signal conductors spaced apart from each other on a partially removed region of the signal conductor at a central portion of the base resistive film. It is composed of:
［作 用 ］
本発明によれば、直流バイアス電流は、信号導体膜の両
端中央部に設けられた下地抵抗膜に対するバイパス導電
路を介し、はとんど減衰を受けることなく通過でき、他
方、発振に寄与する高周波成分のみが抵抗膜を通り減衰
せしめられるので、直流バイアスを低下させることなき
発振防止回路が構成される。[Function] According to the present invention, the DC bias current can pass through the bypass conductive path to the underlying resistive film provided at the center of both ends of the signal conductor film without being attenuated; Since only the high frequency components contributing to oscillation pass through the resistive film and are attenuated, an oscillation prevention circuit is constructed without reducing the DC bias.
［実施例］ 次に、本発明について図面を参照して詳細に説明する。[Example] Next, the present invention will be explained in detail with reference to the drawings.
第１図 ｆａｌおよび（ｂｌはそれぞれ本発明の一実施
例を示す発振防止回路の平面図およびそのｘ−ｘ’断面
図である。本実施例によれば、発振防止回路は、従来と
同じく誘電体基板３上に形成される発振径路の信号導体
膜１の一部を分離し下部の抵抗膜を露出させることによ
って、帰還Ｍ減衰用の下地抵抗膜２を信号導体膜１間に
挿入すると共に、更にこの分離した信号導体膜１の端部
の中央部を接続導体５で架橋接続することによって形成
される。FIG. 1 fal and (bl are respectively a plan view and an x-x' cross-sectional view of an oscillation prevention circuit showing one embodiment of the present invention. According to this embodiment, the oscillation prevention circuit is a dielectric By separating a part of the signal conductor film 1 of the oscillation path formed on the body substrate 3 and exposing the lower resistive film, the base resistive film 2 for feedback M attenuation is inserted between the signal conductor films 1. , and is further formed by cross-linking the center portions of the ends of the separated signal conductor film 1 with a connecting conductor 5.
−Ｍに良く知られているように、導体膜中の高周波電流
は導体膜の縁端部に沿うように分布し、中央部にはほと
んど流れない性質をもつ。As is well known in the art, high-frequency current in a conductor film is distributed along the edges of the conductor film, and has a property that almost no current flows in the center.
従って、上記実施例の信号導体膜１内の高周波電流も当
然これと全く同じ電流分布を示す。Therefore, the high frequency current within the signal conductor film 1 of the above embodiment naturally exhibits exactly the same current distribution.
第２図は上記実施例における信号導体膜の高周波電流分
布を接地導体の高周波電流分布と共に示す第１図（ａ）
のＹ−Ｙ’断面図である。すなわち、信号導体膜１の膜
幅Ｗの中央部を高周波電流軸ｉの原点（ｘ＝０１にとる
と、信号導体膜１を流れる高周波電流ｉ、は原点（ｘ＝
０）で最小となり、縁端部（ｘ ＝ Ｗ／ ２．−Ｗ／
２）で最大となる。このとき接地導体４上の高周波電
流１２は当然のことながらこれとは全く逆となる。Fig. 2 shows the high frequency current distribution of the signal conductor film in the above embodiment together with the high frequency current distribution of the ground conductor as shown in Fig. 1(a).
It is a YY' sectional view of . That is, if the center of the film width W of the signal conductor film 1 is taken as the origin (x=01) of the high frequency current axis i, the high frequency current i flowing through the signal conductor film 1 is set at the origin (x=01).
0), and the edge (x = W/ 2.-W/
2) is the maximum. At this time, the high frequency current 12 on the ground conductor 4 naturally becomes completely opposite to this.
従って、分離した信号導体膜ｌの両端中央部を架橋接続
した接続導体５には高周波電流はほとんど通らないこと
となり、言わば直流バイアス電流のためのバイパス導電
路としてのみ機能し得るようになる。すなわち、高周波
電流および直流バイアス電流の双方に対してそれぞれ独
立の通過路が形成されるので、直流バイアスを低下させ
ることなき発振防止回路として機能することができる。Therefore, almost no high-frequency current passes through the connection conductor 5, which bridge-connects the center portions of both ends of the separated signal conductor film l, and can function only as a bypass conduction path for the DC bias current. That is, since independent passage paths are formed for both the high frequency current and the DC bias current, it is possible to function as an oscillation prevention circuit without reducing the DC bias.
第３図 （ａｔおよびｆｂｌはそれぞれ本発明の他の実
施例を示す発振防止回路の平面図およびそのＹ−Ｙ’断
面図である。本実施例によれば、信号導体膜１の一部は
、高周波電流の最も流れにくい中央部のみを残して下地
抵抗膜２上から切除される。本実施例では残された信号
導体膜１の中央部が直流バイアス電流のバイパス導体と
して機能する。この回路構造は前記実施例に比べ、組立
の接続工数を低減できる利点がある。FIG. 3 (at and fbl are a plan view and a YY' cross-sectional view, respectively, of an oscillation prevention circuit showing another embodiment of the present invention. According to this embodiment, a part of the signal conductor film 1 is , is removed from the base resistive film 2, leaving only the central part where high-frequency current is least likely to flow.In this embodiment, the remaining central part of the signal conductor film 1 functions as a bypass conductor for the DC bias current.This circuit The structure has the advantage that the number of connection steps for assembly can be reduced compared to the previous embodiment.
［発明の効果〕
以上詳細に説明したように、本発明によれば、発振径路
の帰還量減衰用の下地抵抗膜に対するバイパス導電路が
高周波電流分布の最も少ない両端中央部を結んで設けら
れるので、抵抗膜上の高周波電流の流れに対しほとんど
影響を与えることなく、所要の直流バイアス直流をこの
バイパス導電路を介し全く独立に流すことができる。従
って、従来の如く直流バイアス機能を低下させることな
き発振防止用回路を備えた高周波用混成集積回路装置を
容易に実現することができる。[Effects of the Invention] As described above in detail, according to the present invention, the bypass conductive path for the base resistive film for attenuating the amount of feedback of the oscillation path is provided by connecting the center portions of both ends where the high-frequency current distribution is least. The required direct current bias direct current can be made to flow completely independently through this bypass conductive path without having almost any effect on the flow of high frequency current on the resistive film. Therefore, it is possible to easily realize a high-frequency hybrid integrated circuit device equipped with an oscillation prevention circuit without degrading the DC bias function as in the prior art.
第１図 （ａ）および（ｂｌはそれぞれ本発明の一実施
例を示す発振防止回路の平面図およびそのｘ−ｘ’断面
図、第２図は上記実施例における信号導体膜の高周波電
流分布を接地導体の高周波電流分布と共に示す第１図ｆ
ａｌのＹ−Ｙ’断面図、第３図 （ａｌおよび（ｂｌは
それぞれ本発明の他の実施例を示す発振防止回路の平面
図およびそのＹ−Ｙ’断面図、第４図および第５図はそ
れぞれ従来の高周波混成集積回路装置の発振防止回路の
断面構造図である。
１・・−信号導体膜、
２・・・（帰還量減衰用の）下地抵抗膜、３・・・誘電
体基板、 ４・−・接地導体、５・・・接続導体。
第３図
第。図 第５図
ヘ
株Figure 1 (a) and (bl) are a plan view and a cross-sectional view of the oscillation prevention circuit showing an embodiment of the present invention, respectively, and Figure 2 shows the high-frequency current distribution of the signal conductor film in the above embodiment. Figure 1f shows the high-frequency current distribution of the ground conductor.
A Y-Y' sectional view of al, FIG. 3 (al and (bl are respectively a plan view of an oscillation prevention circuit showing another embodiment of the present invention and a Y-Y' sectional view thereof, FIGS. 4 and 5) are respectively cross-sectional structural diagrams of oscillation prevention circuits of conventional high-frequency hybrid integrated circuit devices. 1...-signal conductor film, 2... Base resistive film (for feedback attenuation), 3... Dielectric substrate , 4...Grounding conductor, 5...Connecting conductor.
Claims (1)
号導体膜と、該信号導体膜と高周波信号線路を構成する
前記誘電体基板裏面上の接地導体とを含み、前記高周波
信号線路の発振径路には前記信号導体の一部切除領域と
、前記信号導体の一部切除領域上に露出する下地抵抗膜
と、前記信号導体の一部切除領域上の互いに離間する２
つの信号導体間を端部中央部で接続する前記下地抵抗膜
のバイパス導電路とからなる発振防止回路が形成される
ことを特徴とする高周波用混成集積回路装置。The high frequency signal line includes a dielectric substrate, a signal conductor film formed on one main surface of the dielectric substrate, and a ground conductor on the back surface of the dielectric substrate that constitutes the signal conductor film and a high frequency signal line. The oscillation path includes a partially cut region of the signal conductor, a base resistive film exposed on the partially cut region of the signal conductor, and two parts spaced apart from each other on the partially cut region of the signal conductor.
1. A high-frequency hybrid integrated circuit device, characterized in that an oscillation prevention circuit is formed, comprising a bypass conductive path of the base resistive film connecting two signal conductors at the center of their ends.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327749A JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2327749A JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04192902A true JPH04192902A (en) | 1992-07-13 |
| JP2747112B2 JP2747112B2 (en) | 1998-05-06 |
Family
ID=18202555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2327749A Expired - Fee Related JP2747112B2 (en) | 1990-11-27 | 1990-11-27 | High frequency hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2747112B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004013928A1 (en) * | 2002-08-01 | 2004-02-12 | Matsushita Electric Industrial Co., Ltd. | Transmission line and semiconductor integrated circuit device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797201A (en) * | 1980-12-09 | 1982-06-16 | Fujitsu Ltd | Integrated circuit for microwave |
| JPS5952901A (en) * | 1982-09-18 | 1984-03-27 | Mitsubishi Electric Corp | Microstrip line circuit device |
| JPS60206202A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Bias pattern of microwave circuit |
| JPH02166803A (en) * | 1988-12-20 | 1990-06-27 | Matsushita Electric Ind Co Ltd | Microwave integrated circuit |
-
1990
- 1990-11-27 JP JP2327749A patent/JP2747112B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5797201A (en) * | 1980-12-09 | 1982-06-16 | Fujitsu Ltd | Integrated circuit for microwave |
| JPS5952901A (en) * | 1982-09-18 | 1984-03-27 | Mitsubishi Electric Corp | Microstrip line circuit device |
| JPS60206202A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Bias pattern of microwave circuit |
| JPH02166803A (en) * | 1988-12-20 | 1990-06-27 | Matsushita Electric Ind Co Ltd | Microwave integrated circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004013928A1 (en) * | 2002-08-01 | 2004-02-12 | Matsushita Electric Industrial Co., Ltd. | Transmission line and semiconductor integrated circuit device |
| US6946934B2 (en) | 2002-08-01 | 2005-09-20 | Matsushita Electric Industrial Co., Ltd. | Transmission line and semiconductor integrated circuit device |
| US7088204B2 (en) | 2002-08-01 | 2006-08-08 | Matsushita Electric Industrial Co., Ltd. | Transmission line and semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2747112B2 (en) | 1998-05-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |