JPH0419592B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The image data of the area to be processed in the image memory is read out in word units, and the boundary data of that area is also read out in word units to perform noise removal, contour extraction,
It allows processes such as direction code detection and histogram creation to be performed in parallel, and enables high-speed processing of image data in character recognition, graphic recognition, etc.

[Industrial Application Field] The present invention relates to a high-speed image processing circuit that processes image data at high speed in character recognition, graphic recognition, etc.

In processing devices such as character recognition and figure recognition,
Two-dimensional image data is temporarily stored in image memory and preprocessed such as noise removal. Next, feature quantities are obtained by contour extraction, direction code detection, histogram creation, etc., and characters or figures are created based on the feature quantities. It is something that performs recognition. Therefore, there is a demand for faster processing for determining feature amounts.

[Conventional technology]

The image memory in conventional processing devices that perform character recognition, figure recognition, etc. is accessed in accordance with the raster scan method, and image data is accessed in units of pixels or in units of words, with each word corresponding to multiple pixels. A configuration in which writing and reading were performed was common. In a configuration that writes and reads image data in units of words, serial image data obtained by reading scanning is converted into parallel image data in units of words and written, and the image data read out in units of words is converted into parallel image data in units of words. The data was converted into serial image data and processed.

In addition, for processing such as noise removal, contour extraction, and direction code detection, a shift register with the number of lines corresponding to the size of the processing area is provided, and the image data read from the image memory is stored in the shift register to correspond to the processing area. This is to perform arithmetic processing on the output data of the shift register. For example, when performing noise removal by processing 3 x 3 pixels, a shift register for 3 lines is provided, and 3 x 3 pixels from the outputs of three successive stages of the shift register for each line are used.
If the central pixel is an isolated black dot, it is treated as noise and treated as a white dot.
This is performed sequentially for ×3 pixels.

When performing contour extraction, it is determined whether the center pixel of 3×3 pixels is a conversion point from a white pixel to a black pixel or from a black pixel to a white pixel. Each 3×3 pixel is identified and the contour is determined by a continuous line of conversion points.

[Problem that the invention seeks to solve]

In conventional processing devices such as character recognition or figure recognition, even if image data is written to and read from the image memory in word units, processes such as noise removal and contour extraction are performed in pixel units. Therefore, as the number of image differences increases, the processing time becomes extremely long.

Also, when performing local processing of image data stored in the image memory, it is necessary to change the length of the shift register compared to when processing the entire screen; cannot be easily performed, so it has been difficult to realize a configuration that performs local processing.

The present invention improves the above-mentioned conventional drawbacks, and aims to process image data at high speed by handling image data in word units and performing parallel arithmetic processing.

[Means for solving problems]

The high-speed image processing circuit of the present invention reads image data of a processing area and boundary data of the boundary of the processing area from an image memory in word units, and performs parallel calculation processing, see FIG. 1. and explain.

The image data read by scanning characters, figures, etc. is stored in the image memory 1, and the image data read from the image memory 1 by scanning horizontally in units of words and sequentially in the vertical direction is shifted in units of words. a first shift register 2 that forms image data of a processing area; and second and third shift registers that read and shift boundary data arranged in the vertical direction on both sides of the processing area from the image memory 1 in word units. An arithmetic processing unit 5 that processes in parallel each processing block formed by combining the shift registers 3 and 4 and the output data of each stage of the first, second, and third shift registers 2, 3, and 4, respectively. and a register 6 for accumulating the arithmetic processing output data corresponding to the processing block of the arithmetic processing section 5.

[Effect]

The shift register 2 stores image data read from the image memory word by word in the direction perpendicular to the line direction, and the image data of the processing area is read out and processed by the arithmetic processing unit 5 for noise removal, contour extraction, Processing such as direction code detection and histogram creation is performed. In that case, it may be necessary to perform arithmetic processing using image data adjacent to the area due to the image data accumulated in the shift register 2, so the shift register 3,
This should be stored in 4. Thereby, image data can be accumulated in the shift register 2 in units of words, and processing of a predetermined area can be continued. Furthermore, since the arithmetic processing unit 5 performs arithmetic processing in parallel, high-speed processing is possible.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention. Reference numerals 11 to 22 are registers, and CKT1 to CKT8 are circuits for performing logical filter processing such as noise removal, contour extraction, and direction code detection. Also register 1
1, 12, and 13 constitute a shift register 2, registers 14, 15, and 16 constitute a shift register 3, and registers 17, 18, and 19 constitute a shift register 4. Further, the circuits CKT1 to CKT8 constitute an arithmetic processing section 5 in which 8 pixels correspond to one word. Note that the image memory 1 in FIG. 1 is omitted from illustration.

FIG. 3 is an explanatory diagram of readout control of the image memory,
Eight pixels on each line constitute one word, and the word W1 of line 1 is read out first and the register 11 is read out.
Word W1 on line 2 is then read and applied to register 11, and the contents of register 11 are shifted into register 12. Word W1 on line 3 is then read out to register 11.
and the contents of register 12 are added to register 13
Also, the contents of register 11 are shifted into register 12, respectively. That is, image data is read out word by word in the vertical direction of the image memory, and line 1
-3 words W1 are accumulated in shift registers 11-13 to form image data of an 8x3 (pixel) processing area.

Lines 1 to 8 are border data adjacent to the left side of the word W1 area of lines 1 to 3.
Image data for one word of pixel 0 of (LW1) is written to the shift register 14. In this case, the image data is selected as all-white or all-black image data depending on the initial conditions. Also register 11
According to the word-by-word shift operation in steps 13 to 13, pixel data for one pixel is sequentially shifted from register 14 to registers 15 and 16.

Also, one word worth of image data of lines 1 to 8 (LW1) and pixel 9 is written to the register 17 as boundary data adjacent to the right side of the area. One pixel worth of image data is shifted to registers 18 and 19 from then on. Here, the memory is divided into an area for storing one word of image data and an area for storing boundary data, and the boundary data is read out once every time eight words of image data are read out. controlled by.

For example, register 11 contains the word W on line 4.
1. With the word W1 of line 3 shifted into register 12 and the word W1 of line 2 shifted into register 13, circuit CKT1 contains register 1.
3×3 data consisting of the output data of 4 to 16, each two stages of registers 11 to 13, and the output data are input to the circuit CKT2.
3x3 data of the output data of the stage is input, and in the same way, 3x3 data is input to each circuit CKT3 to CKT7.
3 data is input, and 3×3 data of the output data of the lower two stages of the registers 17 to 13 and the output data of the registers 17 to 19 are input to the circuit CKT8.

Therefore, the pixel data of pixels 1 to 3 on lines 2 to 4 surrounded by the dotted line in FIG. 3 are input to the circuit CKT2, and the pixel data of pixels 2 to 4 surrounded by the dotted line in FIG. 3 are input to the circuit CKT2. Pixel data 7 to 9 are input. That is, each circuit CKT1 to CKT8 has 3×
A processing block of 3 (pixels) is input. In this case, for example, if registers 17 to 19 are not provided, boundary data cannot be used, so
This means that the area including pixels 7 to 9 cannot be processed.

Processing for 3×3 pixels is performed in parallel by each circuit CKT1 to CKT8, and the eight processing results are written to register 20, and registers 21, 2
2, boundary output data of the outputs of the circuits KCT1 and CKT8 is written. Also, each circuit CKT1 to CKT8
is configured to perform logical operations such as addition and multiplication that correspond to logical filter processing, or is a read-only memory that inputs 3x3 image data as an address and obtains a logical filter output corresponding to the address input. It is something that can be configured.

When the processing for word W1 of lines 6 to 8 is completed, the image data of pixel 0 of lines 9 to 17 (LW2) is written to the register 14, and at that point, the image data of pixel 0 of lines 7 and 8 is This means that the data remains in registers 15 and 16. Also, the image data of pixel 9 of lines 9 to 17 (LW2) is written to register 17, and at that point, the image data of pixel 9 of lines 7 and 8 is written to registers 18 and 1.
9 remains. Also, the image data of word W1 on line 9 is written into register 11, and the image data of word W1 on lines 7 and 8 at that time remains in registers 12 and 13. Therefore, it becomes possible to process word W1 on lines 7-9.

When the processing for word W1 of the final line is completed, processing for word W2 of lines 1 to 8 is performed, and in that case, the image data of pixel 8 of lines 1 to 8 (LW1) is stored in the register 14 at the boundary. The image data of the pixels 17 of lines 1 to 8 (LW1) is written to the register 17 as boundary data.

Through the above processing, image data is read from the image memory in word units, and logical filters such as noise removal, contour extraction, and direction code detection are performed by parallel processing, and the processing results are outputted in word units via the register 20. be done.

FIG. 4 is a block diagram of the main part of another embodiment of the present invention. This embodiment shows the case of creating a histogram, and CKT9 indicates "1" of one word of image data.
CKT10 is a circuit consisting of an adder circuit or an encoder that calculates the sum of (black pixels), CKT10 is a circuit consisting of an adder circuit or encoder that corresponds to the image data of one word, 23 is a register, and the same reference numerals as in FIG. They show the same parts.

FIG. 5 is an explanatory diagram of a histogram, showing vertical and horizontal histograms for "mountains" of characters. The sum of "1" (black pixels) of the one word of image data shifted to the register 12 in FIG. By adding, a horizontal histogram is created.

Also, the image data shifted to the register 13,
When the circuit CKT10 adds bitwise, outputs the addition result via register 23, and accumulates bitwise, a vertical histogram is created. Therefore, it is possible to simultaneously obtain vertical and horizontal histograms by word-by-word processing.

Note that the outputs of any of the registers 11 to 13 may be applied to the circuits CKT9 and CKT10, and it is also possible to create a histogram in parallel with the logical filter processing such as the contour extraction described above. Furthermore, although the case where one word is 8 bits is shown, it is also possible to process 16 bits or 32 bits as one word depending on the bit configuration of the circuits CKT1 to CKT10. Also circuit CKT1~CKT
The ten functions can also be implemented by a processor.

Furthermore, it is possible to perform logical filter processing not only on binary image data but also on multi-image image data using similar means.

〔Effect of the invention〕

As explained above, the present invention provides image memory 1
The word-by-word image data in the horizontal direction is sequentially scanned and read out in the vertical direction, and the word-by-word image data is shifted by the first shift register 2 in word units, for example, into a processing area of 8×3 (pixels). The boundary data arranged in the vertical direction on both sides of the processing area is read out in word units from the image memory 1, and the second and third
is shifted by shift registers 3 and 4, and the first
~The output data of each stage of the third registers 2 to 4 are combined to form a processing block of, for example, 3×3 (pixels), and each processing block is sent to the arithmetic processing unit 5.
The processing unit 5 performs processing in parallel, and sets the processing output data corresponding to the processing block in the register 6.The processing unit 5 performs processing such as noise removal, contour extraction, direction code detection, and histogram creation in word units. Therefore, the number of stages of the shift registers 2, 3, and 4 can be relatively small, and there is an advantage that high-speed image processing is possible with an economical configuration.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of essential parts of an embodiment of the invention, Fig. 3 is an explanatory diagram of read control of an image memory, and Fig. 4 is another embodiment of the invention. FIG. 5 is a block diagram of a main part of the system, and FIG. 5 is an explanatory diagram of a histogram. 1 is an image memory, 2, 3, 4 are shift registers, 5 is an arithmetic processing unit, 6 is a register, 11 to 23
is a register, and CKT1 to CKT10 are circuits.

Claims (1)

[Claims] 1. Image data in word units in the horizontal direction is sequentially read out from the image memory 1 by scanning in the vertical direction,
A first shift register 2 that shifts in word units to form image data of a processing area; and reads boundary data arranged vertically on both sides of the processing area from the image memory 1 in vertical word units. second and third shift registers 3 and 4 for shifting;
an arithmetic processing section 5 that processes in parallel each processing block formed by combining the output data of each stage 3 and 4; and a register that accumulates arithmetic processing output data corresponding to the processing block of the arithmetic processing section 5. 6. A high-speed image processing circuit characterized by comprising: