JPH0419634B2 - - Google Patents

Abstract

PURPOSE:To prevent the floating of a non-selecting word line due to the coupling between a word line without increasing the number of element by arranging the word line selected by output signal of adjacent address recorder circuit alternately. CONSTITUTION:MOSFETs Q19-22 and Q39-42 for preventing the floating of the word line at a non-selecting time are connected between respective word lines WL1-4 and WL5-8 and the earth potential of the circuit. When one word line coupled with the same output such as an address decoder part NOR1 (or 2) is selected by word line selecting timing signals phix00-11, word lines to which earth potential is applied by the non-selecting signal of the adjacent address decoder part NOR 2 (or 1) are alternately arranged to prevent the floating of the adjacent non-selecting word lines out of three remaining word lines. Namely, the word lines coupled with the adjacent address decoder parts like WL1, WL5, WL2, WL6,... are alternately arranged.

Description

[Detailed Description of the Invention] [Technical Field] This invention relates to a semiconductor memory device.
For example, MOSFETs with relatively large resistance values
A dynamic RAM (Random Access
This technology relates to technology that is effective for semiconductor storage devices such as memory (memory).

[Background technology]

The inventors of the present application have developed the first word line selection circuit.
We have already developed a circuit as shown in the figure. In this circuit, the address decoder section is divided into two in order to minimize the pitch between word lines. That is, the first address decoder section (NOR gate NOR) shown as a representative has four word lines WL1 to
Forms an address decoder output signal that simultaneously selects WL4. This address decoder output signal is transmitted to the gates of transmission gate MOSFETs Q15-Q18 via cut MOSFETs Q11-Q14 to whose gates a power supply voltage Vcc is constantly applied. On the other hand, according to the remaining 2-bit word line selection address signal, the second address decoder section forms four word line selection timing signals φx00 to φx11, which are output to the transmission gates.
The signals are transmitted to word lines WL1 to WL4 through MOSFETs Q15 to Q18, respectively. By doing so, it is possible to match the pitch of the NOR gate circuit NOR etc. constituting the first address decoder section with the pitch of the word line.

Additionally, MOSFETs Q19 to Q2 are connected between each of the word lines WL1 to WL4 and the ground potential of the circuit to prevent the word lines from rising when not selected.
2 is provided. That is, since unselected word lines are lifted up due to coupling with data lines etc. arranged in an intersecting manner, the word line selection timing is transmitted to the gates of MOSFETs Q19 to Q22 via MOSFET Q23 which receives the output signal of the first address decoder section. The timing signal φWLT is supplied with a low level. As a result, when the address decoder output signal is at a high level (selected state), the MOSFET Q23 is in the on state, and together with the low level of the timing signal φWLT, the MOSFET Q19 to
Q22 is turned off. On the other hand, if the address decoder output signal is at a low level (non-selected state), the MOSFET Q23 is turned off, and
It maintains the on state regardless of the low level of the timing signal φWLT. these
The ON state of MOSFETs Q19 to Q22 prevents unselected word lines from floating.

By the way, with the progress of semiconductor technology, elements and wiring formed on a semiconductor substrate are becoming finer. In this case, when focusing on the wiring, the thickness cannot be reduced to prevent step breakage, but the wiring width tends to become narrower and narrower. Therefore, when considering a dynamic RAM such as 1Mbit, the width of the wiring becomes smaller than the thickness, and the spacing between the wiring also becomes narrower, so the parasitic capacitance between word lines running in parallel increases. It becomes impossible to ignore. Therefore, if one of the four word lines is set to the selected state and the remaining three are set to the floating state and low level as described above, the coupling due to the parasitic capacitance will cause the unselected word line to become unselected. The inventor of the present invention has discovered that a new problem arises in that the word line rises.

Therefore, a latch type MOSFET is installed on each word line.
Although it is conceivable to provide a MOSFET, two MOSFETs are required for one word line, which greatly increases the number of elements.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor memory device that prevents unselected word lines from floating due to coupling between word lines without increasing the number of elements.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows. That is, by alternately arranging word lines that are selected by the output signals of adjacent address decoder circuits, the word lines adjacent to the selected word line are always selected by the output signals of the adjacent address decoder circuits. This prevents it from rising up as a non-selected state.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention.

In the example circuit shown in the figure, the n-channel
IGFET (Insulated Gate
This will be explained using the Field Effect Transistor as an example.

As shown as a representative, a 1-bit memory cell MC consists of an information storage capacitor Cs and an address selection MOSFET Qm, and logic "1" or "0" information indicates whether there is a charge in the capacitor Cs or not. is stored in the form of

To read information, turn on MOSFETQm, connect capacitor Cs to the common data line DL, and sense how the potential of data line DL changes depending on the amount of charge accumulated in capacitor Cs. It is carried out by.

Since the memory cells MC are formed small and many memory cells are connected to a common data line DL to form a highly integrated and large capacity memory matrix, the stray capacitance of the capacitor Cs and the common data line DL is reduced.
Regarding the relationship with Co, the ratio of Cs/Co becomes a very small value. Therefore, the change in the potential of the data line DL due to the amount of charge accumulated in the capacitor Cs becomes an extremely small signal.

A dummy cell DC is provided as a reference for detecting such a minute signal. This dummy cell DC is manufactured under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of its capacitor Cd is approximately half that of the capacitor Cs of the memory cell MC. Capacitor Cd is charged to ground potential by MOSFET Qd' prior to addressing.

As mentioned above, the capacitor Cd is
Since the capacitance value is set to approximately half that of Cs, a reference voltage equal to approximately half of the read signal from the memory cell MC is formed.

The sense amplifier SA is a sense amplifier that expands the difference in potential change caused by the above-mentioned addressing into a sensing period determined by the timing signals (sense amplifier control signals) φpa1 and φpa2 (its operation will be described later). Its input/output nodes are coupled to complementary data lines DL, arranged in parallel. The number of memory cells coupled to the complementary data lines DL is made equal to increase detection accuracy, and one dummy cell is coupled to each of the complementary data lines DL. In addition, each memory cell MC
is coupled between one word line WL and one of the complementary pair of data lines. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component appears equally on both data line pairs DL. , are canceled by the differential sense amplifier SA.

In the above addressing, complementary data line pair
A pair of dummy word lines are connected so that when a memory cell MC coupled to one of DL, is selected, a dummy cell DC is always coupled to the other data line.
One of DWL, is selected.

The sense amplifier SA has a pair of cross-connected MOSFETs Q1 and Q2, and differentially amplifies a minute signal appearing on the complementary data line DL by the positive feedback action of these MOSFETs. This positive feedback operation is
The process starts at the same time that MOSFET Q7, which has been made into a relatively small conductance characteristic in two stages, begins to conduct due to the relatively early timing signal φpa1, and the addressing process causes the voltage difference applied to the complementary data line DL to be Based on this, the higher data line potential falls at a slower rate, and the lower one falls at a faster rate, with the difference widening. At this time, the MOSFET Q8, which has a relatively large conductance characteristic, is made conductive by the timing signal φpa2 at a timing when the voltage difference becomes large to a certain extent, so that the lower data line potential rapidly decreases. By operating the sense amplifier SA in two stages in this way,
This prevents the higher potential from dropping. In this way, when the lower potential drops below the threshold voltage of the cross-coupled MOSFET, the positive feedback operation ends, and the higher potential decreases while remaining at a potential lower than the power supply voltage Vcc and higher than the threshold voltage. The lower potential eventually reaches ground potential (0V).

During the above-mentioned addressing, the stored information in the memory cell MC, which is once about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, if the high level drops by more than a certain level with respect to the power supply voltage Vcc, a malfunction will occur where the data will be read as a logic "0" while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR has the function of selectively bootstrapping only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

The data line pair DL, shown as a representative in the figure, constitutes a column switch CW.
It is connected to the common complementary data line pair CDL via MOSFETQ3 and Q4. The same applies to the other representative data line pairs.
It is connected to the common complementary data line pair CDL via MOSFETQ5 and Q6. This common complementary data line pair CDL is connected to the input terminal of a data output buffer DOB including an output amplifier and the output terminal of a data input buffer DIB.

Row decoder and column decoder RC-DCR
receives an internal complementary address signal formed by the address buffer ADB, forms one word line, dummy word line, and column switch selection signals to address memory cells and dummy cells. That is, external address signals AX0 to AXi are taken into the address buffer ADB in synchronization with the timing signal φar generated by the row address strobe signal, and the row decoders R-DCR
At the same time, predetermined word line and dummy word line selection operations are performed using the word line selection timing signal φx. and a timing signal φac formed by the column address strobe signal.
The external address signals AY0 to AYi are taken into the address buffer ADB in synchronization with the column decoder C.
-DCR and performs a data line selection operation using the data line selection timing signal φy.

The timing control circuit TC receives an address strobe signal and a write enable signal supplied from the outside, and forms various timing signals in addition to the representative timing signals shown above.

The refresh control circuit REFC includes, but is not limited to, a timer circuit and an internal row address signal.
It has a built-in counter circuit that forms ax0 to axi, and a refresh signal supplied from an external terminal.
Triggered by REF.

For example, if the refresh signal is kept at a low level for a certain period of time or more, the timer circuit is activated, and the counter circuit is incremented in accordance with the timing signal φ generated by the built-in oscillation circuit (not shown), thereby generating the internal address signal. Generate by switching continuously. This oscillation circuit may include, but is not limited to, a substrate bias voltage generation circuit (not shown).
It is convenient to share the oscillation circuit for configuring.

On the other hand, if the refresh signal is kept at a low level for a relatively short period of time, the timer circuit will not operate and the counter circuit will be incremented in accordance with this refresh signal. Since such an automatic refresh circuit is known from the above-mentioned document, a detailed explanation thereof will be omitted. Note that when the refresh signal is set to low level, the multiplexer MPX is switched to the refresh control circuit REFC side and transmits the internal address signals ax0 to axi to the row address decoder.

FIG. 3 shows a circuit diagram of an embodiment of the row decoder circuit R-DCR in FIG. 2. In the figure, two address decoder sections are shown as representatives.

In this embodiment, the first two address decoder sections (NOR gate NOR1,
NOR2) has four word lines WL1~
An address decoder output signal that simultaneously selects WL4, WL5 to WL8 is formed. These address decoder output signals have supply voltages on their gates.
Cut MOSFET Q1 to which Vcc is constantly applied
Transmission gate MOSFET Q15-Q18, Q35-Q via Q1-Q14, Q31-Q34, respectively
It will be sent to 38 gates. On the other hand, according to the remaining 2-bit word line selection address signal, the second
Four word line selection timing signals φx00 to φx11 are formed by the address decoder section of the transmission gate MOSFETs Q15 to Q18, Q3.
Word lines WL1~ through 5~Q38, respectively.
It is communicated to WL4, WL5 to WL8. By doing so, the pitch of the NOR gate circuit NOR etc. constituting the first address decoder section can be matched with the pitch of the word line.

In addition, each of the above word lines WL1 to WL4, WL5
~ There is a connection between WL8 and the circuit ground potential to prevent the word line from rising when not selected.
MOSFETs Q19 to Q22 and Q39 to Q42 are provided, respectively. That is, since unselected word lines are lifted up due to coupling with intersecting data lines, etc., a predetermined timing signal is applied to the gates of the MOSFETs Q19 to Q22 via the MOSFET Q23 that receives the output signal of the first address decoder section. It provides φWLT.
These MOSFETQ19~Q22,Q39~Q
The on-state of 42 prevents unselected word lines from floating.

Also, the address decoder section NOR1 (or NOR
2), the word line selection timing signals φx00 to φx11
When one word line is selected, in order to prevent the adjacent unselected word line from floating among the remaining three word lines, the unselected signal of the adjacent address decoder unit NOR2 (or NOR1) is Therefore, as described above, the word lines to which the ground potential is applied are arranged alternately. That is, the word lines, such as WL1, WL5, WL2, WL6, . . . , are alternately arranged to be coupled to adjacent address decoder sections.

This allows, for example, the address decoder section
When the output signal of NOR1 outputs a high level selection signal, the word line selection timing signal φx0
The word line WL1 is set by the high level of 0 to φx11.
Any one of the word lines WL4 to WL4 is set to a high level selected state, and the remaining three word lines are set to a floating state low level and set to a non-selected state. At this time, the output signal of the adjacent address decoder section NOR2 becomes low level,
As described above, MOSFETs Q39 to Q42 are turned on, and the word lines WL5 to WL8 are brought to the low level of the ground potential. Therefore, the unselected word line next to the word line selected by the output signal of the address decoder section NOR1 is always latched to the ground potential by the output signal of the other address decoder section NOR2. It does not float due to coupling due to parasitic capacitance between word lines.

〔effect〕

(1) By alternately arranging the word lines connected to two adjacent sets of address decoders, the word line next to the word line to be selected always receives its non-selected output signal. The MOSFET is turned on by , and is fixed to the ground potential. Therefore, it is possible to reliably prevent unselected word lines from floating due to coupling due to parasitic capacitance between word lines.

(2) Since the means for preventing floating of the unselected word line can be constructed from one MOSFET, it is possible to prevent an increase in the number of circuit elements.

(3) Preventing unselected word lines from floating due to capacitive coupling between word lines can be achieved very simply by simply changing the layout of the word lines.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, the refresh circuit may be omitted. In addition, dynamic RAM
Other circuits constituting the circuit can take various embodiments. In addition, the above NOR gate NOR1 and the address decoder section are respectively configured.
NOR2 does not have to be adjacent to each other.

[Application field]

In the above explanation, the invention made by the inventor of the present application was mainly applied to a dynamic RAM, which is the background field of application. It can be widely used in semiconductor memory devices that select the following.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of an address decoder circuit developed prior to the present invention, and FIG. 2 is a circuit diagram showing an example of a dynamic type address decoder circuit developed prior to the present invention.
FIG. 3, a block diagram of the RAM, is a circuit diagram showing a specific embodiment of the row address decoder R-DCR of FIG. 2. MC...Memory cell, DC...Dummy cell, CW
...column switch, SA ... sense amplifier,
AR...Active restore circuit, RC-DCR...
…Row/column decoder, ADB…Address buffer, DOB…Data signal buffer, DIB…
…data input buffer, TC…timing control circuit, MPX…multiplexer, REFC…refresh control circuit.

Claims (1)

[Scope of Claims] 1. A first address decoder circuit that forms selection signals for a plurality of word lines, a second address decoder circuit that forms selection signals for another plurality of word lines,
Multiple transmission gate MOSFETs that electrically connect the word line selection timing signal line and the word line above.
The outputs of the first and second address decoder circuits are applied to the gate of the transmission gate MOSFET, and one MOSFET is provided between each word line and the ground potential point of the circuit, The target word line selected by the output of the address decoder circuit and the target word line selected by the output of the second address decoder circuit are arranged alternately, and the word line is selected by the output of the first address decoder circuit. When selected, the MOSFET connected to the unselected word line based on the output of the second address decoder circuit.
1. A semiconductor memory device characterized in that when the unselected word line is turned on, the unselected word line is fixed at a ground potential of a circuit. 2. Claim 1, characterized in that the word line is connected to the gate of an address selection MOSFET of a memory cell consisting of an information storage capacitor and an address selection MOSFET. semiconductor storage device.