JPH04196919A - phase comparator - Google Patents

Abstract

PURPOSE:To exactly compare phases at a high speed without limiting the pulse width of an input signal by comparing the phases of two input signals after converting them to pulses having the pulse width by one cycle of a high-speed clock signal with a high-speed latch converting circuit. CONSTITUTION:When a reference signal having arbitrary pulse width is turned to a high H level, an output signal Q of a third D flip-flop 10, for example, is turned to the H level synchronously with the high-speed clock signal. At this time, the output signal Q of a fourth D flip-flop 11 is maintained at the H level, as it is and the output signal of a first AND gate 12 is turned to the H level. Then, the output signal Q of the 11 is turned to a low L level synchronously with the next high-speed clock signal, and the output signal of the 12 is turned to the L level. Therefore, the trigger-shaped positive pulse having the pulse width of the high-speed clock signal synchronous to the rise edge of the reference signal can be obtained as the clock signal of a first D flip-flop 3.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is an electronic automatic control PLL (Phas
This relates to a phase comparator, which is one of the components of eLocked (Loop).

2. Description of the Related Art An example of a conventional phase comparator will be described below with reference to the drawings.

FIG. 3 is a circuit diagram of a conventional phase comparator, and FIG. 4 is a time chart showing phase comparison input/output waveforms in FIG.

As shown in FIG. 3, the conventional phase comparator has a signal that is always at a high (H) level as a D input, a reference signal that is input from a reference signal input terminal 1 as a clock input, and a first signal that will be described later as a reset input. A first D flip-flop 3 inputs the reset signal of the NOR gate 5 and outputs the Q output signal to the comparison output P terminal 7, a signal that is always at a high (H) level as the D input, and a VCO $ input as the clock input. A second D flip-flop 4 receives a VCO output signal input from an input terminal 2 and a reset signal of a second NOR gate 6, which will be described later, as a reset input, and outputs a Q output signal to a comparison output N terminal 8. , ■ Input the CO output signal and the Q output signal of the second D flip-flop 4, and
The first N outputs the flip-flop 3 heliset signal.
The reference signal and the Q output signal of the first D flip-flop 3 are input to the OR gate 5, and the Q output signal of the first D flip-flop 3 is inputted to the OR gate 5.
A second NOR gate 6 outputs a heliset signal.

The operation of the phase comparator constructed as above will be explained below with reference to the time chart of FIG. 4.

First, when the rising edge of the reference signal is ahead of the rising edge of the vCO output signal, the Q output signal of the first D flip-flop 3 becomes high (H) level at the rising edge of the reference signal.

Then, when the next rising edge of the vCO output signal comes, a reset is applied through the first NOR gate 5, and the Q output signal of the first D flip-flop 3 becomes low (L) level. At this time, the Q output signal of the second D flip-flop 4 is reset through the second NOR gate 6 and becomes low (L) since the first output signal of the first D flip-flop 3 is at a high (H) level. keep level.

Conversely, if the rising edge of the reference signal lags behind the rising edge of the CO output signal, the Q output signal of the second D flip-flop 4 goes to the /'% high (H) level at the rising edge of the vCO output signal. Then, when the rising edge of the reference signal is detected, the second NOR gate 6
After that, the second D flip-flop 4 is reset.
The Q output signal of becomes low (L) level. At this time, since the Q output signal of the second D flip-flop 4 is at a high (H) level, the first D flip-flop 3
It is reset through OR gate 5 and maintained at low (L) level.

In this way, the outputs of the D flip-flop tubes 3 and 4 output positive pulses having a width equal to the phase difference between the input signals.

Problems to be Solved by the Invention However, in the above conventional configuration, as shown in FIG.
If a large difference occurs between the two input signal pulse widths, for example, the positive pulse width of the reference signal is larger than the negative pulse width of the CO output signal, and the negative pulse has sunk in, the rising portion of both pulses As a result, a rising edge cannot be detected and a comparison output signal is no longer generated.Therefore, there is a problem in that the pulse width is limited as a condition for the input signal.

The present invention solves the above-mentioned conventional problems, and aims to provide a phase comparator that can accurately perform high-speed comparison for all comparison input signals without imposing any restrictions on the input pulse width. It is.

Means for Solving the Problems In order to solve the above problems, the phase comparator of the present invention is a high-speed comparator composed of a D flip-flop and an AND gate that converts two input signals whose phases are to be compared into trigger-like pulses. a latch conversion circuit; two D flip-flops each inputting two input conversion signals converted into trigger-like pulses by the high-speed latch conversion circuit as clock signals and outputting the output as a comparison output signal; It is provided with two NOR gates that input the comparison output signal and the input conversion signal of the D flip-flop and generate reset signals for each D flip-flop.

Effect With the above configuration, two input signals are converted into trigger-like pulses by the high-speed latch conversion circuit regardless of the input pulse width, and when a phase shift occurs in the input signals, the progress of the two input signals relative to each other is changed. Accordingly, comparison output signals having pulse widths corresponding to the phase differences are output from different D flip-flops.

EXAMPLE Hereinafter, an example of the present invention will be described based on the drawings. It should be noted that the same components as those of the conventional example shown in FIG.

FIG. 1 is a circuit diagram of a phase comparator in an embodiment of the present invention, and FIG. 2 is a time chart showing the high-speed latch conversion input/output waveforms of FIG. 1.

The phase comparator of the present invention has a high-speed latch conversion circuit added between the input terminal 1.2 and the D flip-flop 3.4 of the conventional example.

The high-speed latch conversion circuit includes a third D flip-flop IO that receives a reference signal as a data (D) input, a high-speed clock signal inputted from a high-speed clock input terminal 9 as a clock (CK) input, and a third D flip-flop IO as a data input. 3D
The Q output signal of the flip-flop 10, the fourth D flip-flop 11 which receives the high-speed clock signal as a clock input, the Q output signal of the third D flip-flop 10, and the Q output signal of the fourth D flip-flop 11. a first AND gate 12 which inputs the CO output signal as a data input and outputs the output as a clock signal to the first D flip-flop 3, and a fifth D flip-flop which inputs the CO output signal as a data input and the high speed clock signal as a clock input. P14
, a sixth D flip-flop 15 which receives the Q output signal of the fifth D flip-flop 14 as a data input, and receives the above-mentioned high-speed clock signal as a clock input;
A second D flip-flop inputs the Q output signal of the flip-flop 14 and the Q output signal of the sixth D flip-flop 15, and outputs the output as a clock signal to the second D flip-flop 4.
and an AND gate 16.

−
The operation will be explained with reference to FIG.

First, when the reference signal having an arbitrary pulse width becomes high (H) level, the Q output signal of the third D flip-flop 10 becomes high (H) level in synchronization with the high speed clock signal. At this time, the Q output signal of the fourth D flip-flop 11 still remains at high (H) level, and the first AN
The output signal of the D gate 12 becomes high (H) level. Then, in synchronization with the next high-speed clock signal, the Q output signal of the fourth D flip-flop 11 becomes low (L) level,
The output signal of the first AND gate 12 becomes low (L) level. Therefore, a trigger-like positive pulse having the pulse width of the high speed clock signal and synchronized with the rising edge of the reference signal is obtained as the clock signal of the first D flip-flop 3. Similarly, the fifth and sixth D flip-flops 14.15 and the second AND gate 16 generate a trigger-like positive pulse having the pulse width of the high-speed clock signal in synchronization with the rising edge of the vCO output signal. It is obtained as a clock signal for the second D flip-flop 4.

As explained in the conventional example, the subsequent operation as a phase comparator is performed at the rising edge of both pulses output from the high-speed latch conversion circuit, and the output signal having a pulse width equal to the phase difference between the two pulses is compared. It can be obtained at the output P terminal 7 and the comparison output N terminal 8.

As described above, according to this embodiment, the two input signals whose phases are to be compared are converted into pulses having a pulse width equivalent to one period of the high-speed clock signal by the high-speed latch conversion circuit, and then the phases are compared. Fast and accurate phase comparison can be performed without being limited by the pulse width of the input signal.

Effects of the Invention As described above, according to the present invention, by providing a high-speed latch conversion circuit composed of a D flip-flop and an AND gate at the input stage of a phase comparator circuit composed of two D flip-flops and an AND gate, It is possible to realize an excellent phase comparator that can perform accurate high-speed comparison without being limited by the pulse width of the input signal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a phase comparator in an embodiment of the present invention, FIG. 2 is a time chart showing phase comparison input/output waveforms in FIG. 1, and FIG. 3 is a circuit diagram of a conventional phase comparator. FIG. 4 is a time chart showing the phase comparison input/output waveforms of FIG. 3, and FIG. 5 is a time chart showing the phase comparison input/output waveforms to explain the problems of the conventional example. 1... Reference signal input terminal, 2... vCO output input terminal, 3. 4. 1G, 11. 14. 15...
・D flip-flop, 5, 6...NOR gate, 7
...Comparison output N terminal, 8...Comparison output N terminal, 9.
...High speed clock input terminal, 12, 16...AND gate, L...High speed latch conversion circuit. Agent Yoshihiro Morimoto Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] 1. A high-speed latch conversion circuit composed of a D flip-flop and an AND gate that converts two input signals to be phase-compared into trigger-like pulses, and 2. Two D flip-flops each input one input conversion signal as a clock signal and output the output as a comparison output signal, and input the comparison output signal and the input conversion signal of each D flip-flop, and A phase comparator with two NOR gates to generate a reset signal for the D flip-flop.