JPH0419824U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a time chart of FIG. 1, FIG. 3 is a block diagram of a select signal generation circuit, and FIG. 4 is a block diagram of a selector circuit. In the figure, 1 is a shift register, 2 is a select signal generation circuit, 3 is a selector circuit, and 4 is a logic circuit.

Claims (1)

[Claims for Utility Model Registration] A clock that creates an internal clock SYNC _m having a frequency m times that of the synchronization signal from an input system clock SCLK and a synchronization signal SYNC that distinguishes blocks of data synchronized with the clock. A generating circuit that shifts the synchronization signal using a system clock.
・An a-bit shift register 1 and a quotient obtained by counting the length of the synchronizing signal using the system clock and dividing the counted value A by the multiplication number m (
a select signal generation circuit 2 for calculating M=A/m); a selector circuit 3 for selecting parallel outputs of the shift register at each value of an arithmetic series with the quotient M as a tolerance in the first term 1; and a logic circuit 4 for alternately inverting the internal clock _{SYNC_m} with edges appearing in order at the output of the clock.