JPH044429U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of the frequency multiplier of this invention, Fig. 2 is a time chart showing an example of pulse signals obtained at each part, and Fig. 3 is a block diagram showing an example of the frequency multiplier of this invention.
The block diagrams of FIGS. 4 and 5 showing an example of a conventional frequency multiplier are time charts showing examples of pulse signals obtained in each part of the frequency multiplier.

Claims (1)

[Scope of Claim for Utility Model Registration] A frequency dividing circuit that divides the frequency of the original clock to 1/A, and a frequency sufficiently lower than the frequency of the output clock of the frequency dividing circuit, and a pulse width that is lower than the frequency of the output clock of the frequency dividing circuit. an input pulse signal whose frequency and pulse width vary within a range sufficiently greater than the pulse width;
synchronized with the output clock of the frequency divider circuit from the output clock of the frequency divider circuit and the original clock;
and a retiming circuit that obtains a pulse signal whose pulse width is equal to the pulse width of the input pulse signal, and a pulse number N of the output clock of the frequency dividing circuit within the period of the pulse width of the pulse signal output from the retiming circuit. A frequency multiplier comprising: a counter for counting; and a frequency dividing circuit for dividing the frequency of the original clock by 1/N according to the count value of the counter.