JPH0419896A - Refresh method for dynamic memory - Google Patents

Abstract

PURPOSE:To shorten time for a refresh processing by executing RAS only refresh to a first memory area by executing a read cycle, and executing the RAS only refresh to a second memory area by executing a following write cycle. CONSTITUTION:When designating a refresh space, an address line select circuit 5 applies a refresh space select signal to a control signal generation circuit 9. Corresponding to a data strobe signal, read/write signal, timing signal and refresh space select signal, the control signal generation circuit 9 selectively applies an RAS signal, CAS signal and write enable signal to a DRAM 1. Thus, since the RAS only refresh is executed to the first memory area by designating a row address and the RAS only refresh is executed to the second memory area by designating only the row address without applying any write enable signal when executing the following write cycle, the time for the refresh processing can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for refreshing a dynamic memory.

Among semiconductor memory devices, DRAM (Dynami
cRandom Access Memory) has a structure in which the stored charge in a capacitor is used as stored data, and since data is lost in the form of leakage current as time passes, it is necessary to periodically read out the stored data in the memory cell. A refresh operation is required to amplify and rewrite.

Conventionally, various methods have been adopted to refresh DRAM used in computers, but they can be roughly divided into refresh methods for the computer's central processing unit (Central Processing Unit).
There are two methods: soft refresh, which refreshes by executing a program performed by a Processing Unit (hereinafter abbreviated as CPU), and hard refresh, which refreshes by the operation of a specially provided circuit.
There are different types.

Among them, the most common soft refreshes are:
By specifying an arbitrary memory area in DRAM as a refresh area and performing a pseudo read process on that area, that is, by performing a dummy read, the address signals necessary for refresh and the address signals are This is a RAS-only refresh that refreshes memory cells by generating a row address strobe signal (hereinafter referred to as RAS signal) for taking in a row address signal corresponding to each word line in the memory area.

In the case of soft refresh such as this RAS-only refresh, the memory interface circuit that is interposed between the CPU and DRAM and controls the exchange of signals between them has a configuration that can handle actual data read and write processing. Since the refresh operation can also be handled with just one, no special circuit is required for refresh.

On the other hand, in the case of hard refresh, some circuitry needs to be added because refresh is achieved through processing different from normal data reading and writing.

The program executed by the CPU in the RAS-only refresh described above is divided into a memory cycle in which read access to memory is executed, and an internal cycle in which processing to transfer read data to a data storage register is executed within the CPU. It is the memory cycle that is actually refreshed. In other words, the above RA
The S-only refresh repeats an instruction to read data from memory and store it in a register.

In this case, in the memory cycle, a column address strobe signal (hereinafter referred to as
Since no CAS signal (referred to as a CAS signal) is generated, data is not actually read from the memory cells, and therefore data transfer to the register in the internal cycle is a process that does not involve refresh at all.

FIG. 5 is a flowchart showing the RAS-only refresh program.

Following the start in step n1, in step n2, the address corresponding to the start position of the memory area to be refreshed is set in the indirect register P, and in the next step n3, the number of rows in the memory area to be refreshed, that is, the number of rows in the memory area to be refreshed, For example, 512 is set in the loop counter N as the number of repetitions. This specifies the memory area to be refreshed.

In the next step n4, the row address set in the indirect register P is stored in the dummy register D, a dummy read is executed for the row address in the memory area, and the memory cells on the corresponding word line are refreshed.

In the next step n5, the row address set in the indirect register P is incremented, and in the next step n6, the refresh count N set in the loop counter N is decremented.

In the next step n7, it is determined whether the refresh count N is not O. If it is not 0, the processes of steps n4 to n7 are repeated and a dummy read is executed for the next row address in the memory area. Then, the memory cells on the next word line are refreshed.

By repeating such processing, the specified memory area is sequentially refreshed, and when it is determined in step n7 that the number of refreshes set in the loop counter N is O, that is, the specified memory area is refreshed. When all are completed, the process moves to step n8, and the process ends here.

Problems to be Solved by the Invention However, in the conventional soft refresh described above, the internal cycle processing for transferring data to registers in the program executed by the CPU is not equally involved in refresh, resulting in wasted time. However, there is a problem in that the time required for refreshing is long.

Therefore, it is an object of the present invention to provide a dynamic memory refresh method that can significantly reduce processing time.

Means for Solving the Problems The present invention provides a first refresh memory area.
Following a read cycle in which the first memory area is addressed and data is read, the second memory area is addressed and the first memory area is read. The process of performing a write cycle in which data read from an area is written to a second memory area is performed by specifying only the row address in the read cycle, and by specifying only the row address in the write cycle without giving a write enable signal that specifies the write operation. By specifying only the first and second memory areas, the first and second memory areas are sequentially executed, and the first memory area is refreshed when the read cycle is executed, and the second memory area is refreshed when the write cycle is executed. This is a dynamic memory refresh method characterized by the following.

Effect According to the present invention, RAS-only refresh of the first memory area is performed in execution of a read cycle, and RAS-only refresh of the second memory area is performed in execution of a subsequent write cycle. There is no waste and processing time can be shortened.

Embodiment FIG. 1 is a block diagram showing a schematic configuration of a part of a computer 2 including a DRAM to which a dynamic memory refresh method according to an embodiment of the present invention is applied. The DRAMI to be refreshed is connected to the CPU 4 via the memory interface circuit 3. The memory interface circuit 3 is a circuit for controlling the exchange of signals between the CPU and the DRAM.

FIG. 2 is a block diagram showing a schematic configuration of the memory interface circuit 3. As shown in FIG. The address line selection circuit 5 is a circuit for outputting an address designation signal corresponding to the address signal given from the CPU 4 via the address bus 6. As the address designation signal, a block selection signal is sent via the address bus 7. Further, memory address signals are sent to each DRAMI via another address bus 8. DRAMI is divided into a plurality of blocks, and one of the blocks is selected by the block selection signal.
A block is selected, and an arbitrary address in the selected block is designated by the memory address signal.

Further, in the address line selection circuit 5, the address bus 6
It also has the function of supplying a refresh space selection signal to the control signal generation circuit 9 when the memory area of the DRAMI to be refreshed, that is, the refresh space, is specified from the CPLI 4 via the CPLI 4.

The control signal generation circuit 9 controls the DRAMI in response to a data strobe signal, a read/write signal, a timing signal applied from the CPU 4, and a refresh space selection signal applied from the address line selection circuit 5.
It has a function of selectively providing an AS signal, a CAS signal, and a write enable signal (hereinafter referred to as WE double signal). A response signal is sent to the control signal generation circuit 9 or the CPU 4.

FIG. 3 is a diagram schematically showing a partial memory area of the DRAMI to which the refresh method of the embodiment is applied.

FIG. 4 is a flowchart showing a program of the refresh method of the embodiment executed by the CPU 4. As shown in FIG.

Next, with reference to FIGS. 3 and 4, the procedure of the dynamic memory refresh method of this embodiment will be explained.

The refresh method of this embodiment is a soft refresh performed by executing a program by the CPU 4.

Following the start in step n1, in step n2, a row address, for example "1", corresponding to the starting position of the first memory area to be refreshed is set in the indirect register P,
Furthermore, in the next step n3, the row address r257J corresponding to the start position of the second memory area to be refreshed is
is set in another indirect register Q.

In the next step n4, 256 is set in the loop counter N as the number of rows in the first and second memory areas, that is, the number of refresh repetitions. As a result, the area with row addresses "1" to "r256" is designated as the first memory region to be refreshed, and the row addresses "257" to "r512" are designated as the second memory region.

In the next step n5, a command to read data from the first memory area and write the read data to the second memory area is given from the CPU 4 to the DRAM 2 via the memory interface circuit 3.

At this time, in a read cycle in which data is read from the first memory area, only the RAS signal is outputted as an address strobe signal from the control signal generation circuit 9, and the CAS signal is not outputted. That is, RAS only refresh is performed on the memory cells on the word line corresponding to the row address "1" set in the indirect register P.

Furthermore, even in a write cycle in which data is written to the second memory area, the address strobe signal output from the control signal generation circuit 9 is only the RAS signal, and in this case, even though it is a write cycle, the WE Double signal is not output. That is, in this case, RAS only refresh is performed on the memory cells on the word line corresponding to the row address "r257" set in the indirect register Q.

In the next step n6, the row addresses set in the indirect registers P and Q are incremented, and in the next step n7, the refresh count N set in the loop counter N is decremented.

In the next step n8, it is determined whether the refresh count N is not 0, and if it is not 0, the processes of steps n5 to n8 are repeated, and the refresh count N in the specified first and second memory areas is A read cycle and a write cycle for the next row address are executed to refresh the memory cells on the next word line.

By repeating this process, the specified first and second
The memory areas of are sequentially refreshed, and step n
8, when it is determined that the number of refreshes set in the loop counter N is O, that is, the specified first
and the refresh of the second memory area is 25, respectively.
When all six times are completed, the process moves to step n9, and the process ends here.

In addition, in the refresh method of this embodiment, two memory areas are refreshed in one refresh process, so the number of times one memory area is refreshed is 5 compared to the conventional one.
12, but it is said to be half that, 216.

Effects of the Invention As described above, according to the dynamic memory refresh method of the present invention, RAS-only refresh of the first memory area is performed by specifying only the row address in execution of a read cycle, and RAS-only refresh of the first memory area is performed in execution of a subsequent write cycle. Since the RAS-only refresh of the second memory area is performed by specifying only the row address without applying a write enable signal, there is no waste in the refresh process and the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of a part of a computer including a DRAM to which a dynamic memory refresh method according to an embodiment of the present invention is applied, and FIG. 2 is a configuration of a memory interface circuit in the computer. 3 is a diagram schematically showing the configuration of the DRAM, FIG. 4 is a flowchart showing the procedure of the refresh method, and FIG. 5 is a flowchart showing the procedure of the conventional refresh method. 1...DRAM, 2...Computer, 3.Memory interface, 4...CPU, 5...Address line selection circuit, 9...Control signal generation circuit Agent Patent attorney Number of strokes Keiichi Fig. Diagram

Claims (1)

[Claims] A first memory area and a second memory area are specified as memory areas to be refreshed, and following a read cycle in which an address is specified and data is read from the first memory area, a first memory area and a second memory area are specified as memory areas to be refreshed. The process of performing a write cycle in which the data read from the first memory area is written to the second memory area by specifying an address for the second memory area, and by specifying only the row address in the read cycle. In the cycle, the write operation is sequentially executed in all the first and second memory areas by specifying only the row address without giving the write enable signal that specifies the write operation, and the first memory area is refreshed by executing the read cycle. A dynamic memory refresh method characterized in that a second memory area is refreshed by executing a write cycle.