JPH04199247A - Pseudo memory error generation circuit - Google Patents

Abstract

PURPOSE:To simplify the processing of a pseudo-error by automatically invalidating an inversion instruction at the time of memory writing after a parity bit inverting instruction is issued. CONSTITUTION:By adding a pseudo-error clear circuit 10, a pseudo-error latch 8 is cleared to '0' at the time of memory writing after '1' is set in the pseudo- error latch 8. In other words, a pseudo-error generating instruction is automatically invalidated after one memory cycle. Since the pseudo-error of a memory can be generated only when the error is required, the need of a process for ignoring the other errors is eliminated and error processing is simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diagnostic circuit for a memory device of an information device such as a personal computer or a workstation.

[Conventional technology]

The memory system of general information processing equipment uses parity or FCC (
Error Correcting Code)
Check bits such as these are added to detect errors in the memory contents.

Further, in order to diagnose whether these error detection circuits and the test bit memory storing the test bits are normal, a circuit that generates a pseudo error may be added. For example, in the case of a parity code, a pseudo error can be generated by inverting the polarity of the parity at the time of writing and reading the address.

Such a conventional example is disclosed in Japanese Unexamined Patent Publication No. 63-73437.

[Problem to be solved by the invention]

By the way, when an error occurs in memory, NMI (
Non Maskable Interrupt
) etc. to notify the main CPU.

When an interrupt such as NMI is input, the CPU immediately writes the current internal information to the stack area, and later reads and executes the interrupt processing instruction.

Here, in the conventional technology, there is a problem in that when an instruction is given to generate a pseudo error for diagnosis, the pseudo error continues to occur until the next instruction is given to disable it. That is, the check bit may be inverted when writing memory to the stack area, or an error may occur again when reading an interrupt processing instruction.

Therefore, in interrupt processing, it is necessary to create a program to ignore errors other than the original pseudo errors.
There was a problem that the processing became complicated.

SUMMARY OF THE INVENTION An object of the present invention is to simplify error handling by ensuring that a pseudo error occurs only once as originally required, and by preventing errors from occurring where they are not needed.

[Means to solve the problem]

In order to achieve the above object, the present invention automatically invalidates the pseudo error occurrence instruction after one memory cycle.

For example, in a pseudo error generation method that inverts the check bits during writing and writes them to the test memory, when the first memory write is made after instructing the generation of a pseudo error, the check bit inversion function is disabled, and subsequent writes are disabled. This is to prevent the check bits from being inverted.

Alternatively, in a pseudo-error generation method that inverts check bits or data during read to generate an error, the first memory read after instructing pseudo-error generation disables the check bit or data inversion function,
This is to prevent the bits from being inverted during subsequent reading.

Alternatively, in a pseudo error generation method that generates an error by inverting the output of the error detection circuit itself when reading, the first memory read after issuing a pseudo error generation instruction disables the error detection circuit's output inversion function. This is to prevent the error signal from being inverted during subsequent reading.

[Effect]

Inspection bits and data inversion instructions are normally issued by the main CPU.
It is often controlled by the ■/○ register located in the I/○ space of.

Therefore, in a pseudo-error generation method that inverts the check bits during writing and writes them to the test memory, a memory write end pulse is created from the memory write signal, and when the first memory write after instructing pseudo-error generation occurs, the pulse It is sufficient to clear the I10 register, which instructs inversion.

Alternatively, in a pseudo error generation method that generates an error by inverting the check bit or data during read, a memory read end pulse is created from the memory read signal,
When there is the first memory read after instructing the occurrence of a pseudo error, the I10 register, which instructs inversion, may be cleared by that pulse.

Alternatively, in a pseudo error generation method that generates an error by inverting the error detection signal at the time of reading, a memory read end pulse is created from the memory read signal, and when the first memory read after instructing the generation of a pseudo error occurs, The pulse may be used to clear the I10 register that issues an inversion instruction.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. Note that in order to simplify the explanation, the memory checking method is assumed to be a parity method. In the figure, 1 is a data memory, 2
is a data bus, 3 is a parity memory, 4 is a parity generation circuit, 5 is a parity signal, 6 is a parity check circuit,
7 is a parity error latch. Further, 8 is a pseudo error latch that indicates a pseudo error, 9 is a parity inversion circuit, and 610 is a pseudo error clear circuit which is a unique part of the present invention.

Briefly explain the operation. When, for example, a CPU connected to the data bus 2 performs memory writing, the data itself is written to the data memory 1. At the same time, a parity signal 5 is generated from the write data in a parity generation circuit 4 and written to a parity signal 3. At the time of reading, data is read from the data memory 1, and the parity generation circuit 4 generates a parity signal 5 from the data output to the data bus 2, as in the case of writing, and the parity check circuit 6 generates a parity signal 5.
A comparison is made with the output of parity memory 3.

If the two values are different, it is determined that there is a memory error, the parity error latch 7 latches the error state, and the NMI signal 11 is notified to external devices such as 6) U.

Next, a case in which a pseudo error occurs will be explained. First, prior to writing to the memory, the pseudo error latch 8 is set to °°1. The pseudo error latch 8 may be configured as a general I10 register. Thereafter, when memory writing is performed, the parity signal 5 to be written into the parity memory 3 is inverted by the parity inverting circuit 9. Next, when the written address is read out, an error occurs because the contents of the parity memory 3 are inverted, and the NMI signal 11 is output.

The operation up to this point is the same as that of the prior art. Adding the pseudo error clearing circuit 10, which is a feature of the present invention, clears the pseudo error latch 8 by writing to memory after setting the pseudo error latch 8 to "1".
Make it ゛. The operation is explained using a time chart as shown in Fig. 2.

Here, CLK20 is the basic clock signal, rowc-
N21 is I10 write signal (negative polarity), MWTC-N
22 is a memory write signal (negative polarity), MRDC-N2
3 is a memory read signal (negative polarity), and DATA24 is a data signal. At the rising edge of l0WC-N21 at time t], "1", which is the value of DA and TA24, is written to the pseudo error latch 8. At the subsequent rising edge of MWTC-N22 at time t2.
Data and parity information are written into the data memory 1 and the parity memory 3, respectively. The content of the pseudo error latch 8 is cleared to 0° at time L3 by the pulse of the clear signal 25 generated from the MWT(, -N22) in the pseudo error clearing circuit 10.Therefore, from now on, the content of the pseudo error latch 8 is There is no need to perform the process of returning to ``.'' When the memory is read from the same address that was written next, the data and parity are read out at time t4, the error is latched in the parity error latch 7, and the NMI (
No. 3 11 is output.

As described above, according to the present invention, the inversion instruction is automatically invalidated by memory writing after the parity pit inversion instruction is issued, so that pseudo error handling can be simplified.

FIG. 3 shows an embodiment in which the present invention is applied to a system in which a pseudo error is generated by inverting the parity bit during memory reading.

Unlike the configuration in FIG. 1, parity inversion circuit 9 is connected to the output of parity memory 3. The clear signal 25, which is the output of the pseudo error clear circuit 10, is created from the memory read signal MRD (>N23.The operating principle is based on the first
This is similar to the figure, and by clearing the pseudo error latch 8 that instructs parity inversion at the end of memory reading,
For example, pseudo parity errors can be prevented when reading instructions in an interrupt processing routine. Therefore, the error handling routine only needs to process the errors that are originally required.

Further, a method in which a pseudo error is generated by inverting the output of the parity error latch 7 can be similarly applied.

Although this embodiment has been explained using the parity method, the ECC
The present invention can also be applied to a memory system that performs error correction/detection based on the method.

U Effects of the Invention] According to the present invention, a memory pseudo error can be generated only when it is originally required, so processing such as ignoring other errors is not necessary, and error processing can be simplified. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a timing chart showing its operation, and FIG. 3 is a block diagram of another embodiment of the present invention. 1...Data memory 2...Data bus 3...
・Parity memory 4...Parity generation circuit 5...
・Parity signal 6... Parity check circuit 7゛°゛ Parity error latch 8... Pseudo error latch 9... Parity inversion circuit 1
0...Pseudo error clear circuit 1]...NMT signal 20...CLK21-
10WC-N 22-MWT C-N23...
MRD C-N 24...DATA25...
・Clear Signal Agent Patent Attorney Katsuo Ogawa

Claims (1)

[Claims] 1. A data memory that stores data, a test bit generation circuit that creates test bits from the data when writing, a test bit memory that stores the test bits, and a test bit memory that reads data from the data memory when reading. In the memory system, the memory system includes an error detection circuit that detects an error using the data read from the test bit memory and the test bit read from the test bit memory, the inverting means for inverting the output of the test bit generation circuit during writing; A pseudo memory error generating circuit characterized in that the means is effective only for one memory write after an inversion instruction. 2. A data memory that stores data, a test bit generation circuit that creates test bits from the data when writing, a test bit memory that stores the test bits, and data read from the data memory and the test when reading. In a memory system comprising an error detection circuit that detects errors using the check bits read from a bit memory, the inverting means inverts the output of the check bit memory or the output of the data memory during reading; and the inverting means. A pseudo memory error generating circuit is characterized in that only one memory readout after an inversion instruction is valid. 3. A data memory that stores data, a test bit generation circuit that creates test bits from the data when writing, a test bit memory that stores the test bits, and data read from the data memory and the test when reading. In a memory system comprising an error detection circuit that detects errors using the check bits read from a bit memory, the inverting means inverts the output of the error detection circuit to a value indicating an error at the time of reading, and the inverting means A pseudo memory error generation circuit characterized in that only one memory readout after an inversion instruction is valid.