JPH04199341A - Memory access protective device - Google Patents

Abstract

PURPOSE:To perform memory access protection between mutual processes by limiting an accessible area with the process in address space. CONSTITUTION:An access right management table 3 storing a memory access key corresponding to the address and an access key register 4 holding the memory access key of the current process are provided. An access right decision circuit 2 deciding the accessibility of the address required from a processor 1 with the use of the contents of the access right management table 3 and the access key register 4 is provided. The access space is divided into individually accessible areas for each process, and the accessibility of the process issuing the request against the memory content at the time of issuing memory access request is decided. Thus, the memory access protection is performed between mutual processes at the time of travelling plural processes in one address space.

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to an electronic meter 1' having a processor and a memory.
The present invention relates to a control unit t4 which protects access when a process, which is one of the four basic control points of an operating system, accesses memory in a combination coater. [MoY-Next Technology] Conventionally, a branch of memory access protection control manages the memory space in pages or 1" segment l- in the middle level, and when a memory access request is issued, the memory access is accessed. 71
Access information p1 set for each area including Jerez?
Access is determined by referring to the management table. These days, the access information management table is
Since it only has the success/failure information related to the read, tj, or write corner number, is the protection during memory access limited to the read or write corner? )
I can't. In other words, issuing a memory access request

[
f:r! There is no access request issued from the same process. [Problems to be Solved by the Invention] In the conventional technology, when multiple data parts and stack parts of each process are placed in one address space in order to perform process switching at high speed, they are not connected to each other. There was a problem that the unique data section and stack section could not be protected. The present invention has been made to solve the above problems. An object of the present invention is to provide a technology that can realize mutual memory access protection between processes, which was impossible with conventional technology, when multiple processes run within one address space. . The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] In order to achieve the above object, the present invention provides a memory access protection device that performs memory access protection control between a processor and a memory in an electronic computer having a processor and a memory, comprising: An access right management table that stores memory access keys corresponding to addresses, an access key register that stores the memory access keys of currently running processes, and the contents of the access management table and access key register are used. The most important feature is that it includes an access right determination circuit that determines whether an address requested by a processor can be accessed. [Operation] According to the above-mentioned means, the 71~res space is divided into areas that can be accessed individually by each process, and when a memory access request is issued, the process that issued the request accesses the address indicated by the address. Since it determines whether or not the memory contents can be accessed, when multiple processes are running within one address space, it is possible to protect mutual memory access between processes, which was impossible with conventional technology. be able to. The conventional technology is within the 71~res space. The difference is that the areas that each process can access are limited. [Embodiment of the Invention] An embodiment of the present invention will be specifically described below with reference to the drawings. In addition, in all the figures for explaining the embodiment, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted. FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, in which 1 is a processor (CPU), 2 is an access right determination circuit, 3 is an access right management table, and 4 is an access key register. , 5 is a memory, and 6 is a display device. The access right management table 3 stores memory access keys indicating processes that can access the memory contents indicated by the address. The access key register 4 holds the memory access key of the currently running process. FIG. 2 is a block diagram showing the configuration of the access right determination circuit 2. As shown in FIG. In FIG. 2, 11 is an address sending circuit, which receives an access request address from the processor (CPU) 1 and sends out the address. Reference numeral 12 denotes a memory access key extraction circuit, which extracts a memory access key corresponding to the address from the access request address and applies it to the memory access key comparison port g1.
3. The memory access key comparison circuit 3 compares the memory access key inputted from the memory access key extraction circuit 12 with the memory access key (built in the memory 5) held by the currently running process inputted from the access key register 4. The address sending circuit 11 and the processor (CPU) output a permission signal or a non-permission signal by comparing the data with the previous address (which had previously been issued). The memory access key held by the currently running process, which is set in the access key register 4, is set in the processor (CPU) 1 when the processor starts running. FIG. 3 is a diagram showing the contents of an access information management table taking a page table as an example, and consists of a real address and an attribute consisting of n bits. Among these, the attributes related to access protection are R/W and S/l+ data. ,”10. O
It is expressed as lo,,i/l. S/t, J are data indicating whether or not it is possible to access 1-zamo-1 at any time.For example, if it is 1, it can be accessed from knee-zamo-1, and when it is O, it is possible to access 7 quirks in user mode. He is known for his talent. FIG. 1 is a diagram showing the contents of the habitual human rights management table 3, which is composed of conventional attributes and memoria 9 of m pino [. Next, the operation of this embodiment will be explained. Fig. 5 is a tanu process explaining the processing operation of this embodiment)
The memory access protection device of this embodiment, as shown in FIG. ).If human rights judgment time G2 is sent, refer to access rights management table 3 based on the reply sent to A1, and find A1<'
Obtain the memory access key corresponding to L=S (1
02) Next, compare the obtained memory access key with the contents of the 7 access key register 4 and determine whether access is permitted to the currently running process L4? -i Now (103). If it is determined that the access has been accessed (in the anterior chamber) (, 1, 2y), send the trace to memory 5 (1.04.). Send it to Zenosa 1 (10 iT, ). Access is not allowed.
If it is determined that the Y1 access request is not allowed (disallowed), the A1-Inos is not sent to the memory 5, and the processor 1 is notified that it is an invalid Y1 access request (106). 4(2) As can be seen, in this embodiment (according to this example, each process has an area that can be accessed by each process) (-), memory access request When the request was issued, Seth who issued the request
Since the content of the memory 13 indicated in the response is determined whether it is accessible or not, it is difficult to use the conventional technology when running a multiple memory access. Mutual memory access protection between the bus I-1 processes, which was previously possible, can be realized. Hereinafter, the present invention will be described in detail with reference to Examples C'.
teeth! 4':<, Range 1: ! that does not deviate from the gist. ;
Therefore, according to the present invention, according to the explanation [7. ,a]·
1. 7 in space? Ac1 Nos II by Pu1-1 Seth
7. Don't limit the area where you can function, do you do something like that in the space space without being aware of your own personality? If the address space + i', f function is used, multiple block [
l process 5/placement-4 a) K (protect mutual C' memory access between processes-) 2, etc., 1

[Brief explanation of the drawing]

Figures +-i show the general configuration of the embodiment of the present invention.
Block diagram, Figure 2 N'A-2 Example σ) Access judgment circuit:
Puff) Block M to reduce the configuration, 3rd [Y] is an access page table example! , information tube array (T-pull contents shown in J-figure, number = q [51
1+t, j′ ccess rights control J! of this embodiment! FIG. 5 is a diagram showing a processing flow for explaining the processing operation of this embodiment. In the figure, l Zorocera 1, 27' access right determination circuit, r
3 Access rights management table, 1 Access key L
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Claims (1)

[Claims] (1) A memory access protection device that performs memory access protection control between the processor and memory in an electronic computer having a processor and memory, which includes an access right management table that stores memory access keys corresponding to addresses. , an access key register that holds the memory access key of the currently running process, and an access right that uses the access right management table and the contents of the access key register to determine whether the address requested by the processor can be accessed. A memory access protection device comprising: a determination circuit.