JPH04199514A - Manufacture of semiconductor integrated circuit device - Google Patents

Manufacture of semiconductor integrated circuit device

Info

Publication number
JPH04199514A
JPH04199514A JP33583290A JP33583290A JPH04199514A JP H04199514 A JPH04199514 A JP H04199514A JP 33583290 A JP33583290 A JP 33583290A JP 33583290 A JP33583290 A JP 33583290A JP H04199514 A JPH04199514 A JP H04199514A
Authority
JP
Japan
Prior art keywords
film
etching
etched
mask
metal film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33583290A
Other languages
Japanese (ja)
Inventor
Yoshifumi Takada
佳史 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP33583290A priority Critical patent/JPH04199514A/en
Publication of JPH04199514A publication Critical patent/JPH04199514A/en
Pending legal-status Critical Current

Links

Landscapes

  • Physical Vapour Deposition (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To highly accurately etch a fine pattern by dry-etching with a porous metal film as a mask and patterning a film to be etched. CONSTITUTION:A film 2 to be etched comprising an Si oxide film, an Si nitride film, a polycrystalline Si film or a plurality of these layers is on a semiconductor substrate 1, while a porous metal film 3 is high melting point metal such Ti, TiN, W, their silicide or nitride, or compound in the high melting point metal, which is formed entirely on the film 2 to be etched by means of sputtering, etc. The film 2 is dry-etched with the porous metal film 3 as an etching mask. Thus no ion reflection occurs on the etching mask, so that dry etching conforming to the mask pattern is performed and highly accurate fine processing is possible.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路装置の製造方法に関するもの
であり、特にRIEのようなドライエツチングを行う際
に、マスクパターンに忠実な高精度の微細加工を可能と
する半導体集積回路装置の製造方法に関するものである
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and in particular, when dry etching such as RIE is performed, it is possible to perform high-precision fine etching that is faithful to a mask pattern. The present invention relates to a method for manufacturing a semiconductor integrated circuit device that can be processed.

〔従来の技術〕[Conventional technology]

第2図は従来例における半導体集積回路装置の製造方法
を示す断面図である。1は半導体基板、2は被エツチン
グ膜で例えばSi酸化膜、Sj窒化膜、多結晶Si膜或
いは半導体基板1自身であってもよい。5はフォトレジ
ストであり、被エツチング膜2を形成した後、通常の写
真製版工程を経て所望のフォトレジストパターン5を形
成するものである。
FIG. 2 is a sectional view showing a conventional method for manufacturing a semiconductor integrated circuit device. 1 is a semiconductor substrate, and 2 is a film to be etched, which may be, for example, a Si oxide film, a Sj nitride film, a polycrystalline Si film, or the semiconductor substrate 1 itself. 5 is a photoresist, and after forming the film to be etched 2, a desired photoresist pattern 5 is formed through a normal photolithography process.

この後、RI E (Reactive Jon Et
ching)のようなドライエツチングを行うことによ
って、フォトレジストパターン5をマスクとして、被エ
ツチング膜2のパターニングを行う。
After this, RI E (Reactive Jon Et
Using the photoresist pattern 5 as a mask, the film to be etched 2 is patterned by dry etching such as etching.

フォトレジスト5のパターニングに際しては、フォトレ
ジスト5への入射光とフォトレジスト5と被エツチング
膜2との界面からの反射光との干渉によって定在波か発
生するためにレジストパターン側壁は波打った形状とな
る。エツチングパターンの寸法はレジストパターンの底
部の寸法によって決定されるため、このようにレジスト
パターンの側壁が波打つことはレジストパターン底部の
寸法制御性の劣化を招き、即ち、エツチングパターン底
部の寸法の不安定性を意味する。通常はこのように波打
つ形状を抑えるためにレジストのベーキング焼成を行っ
ている。これによって、レジストパターン5の側壁はな
めらかな形状となり寸法制御性も大幅に改善される。
When patterning the photoresist 5, the side walls of the resist pattern were wavy because standing waves were generated due to interference between the light incident on the photoresist 5 and the light reflected from the interface between the photoresist 5 and the film to be etched 2. It becomes the shape. Since the dimensions of the etching pattern are determined by the dimensions of the bottom of the resist pattern, this waving of the sidewalls of the resist pattern leads to a deterioration in the dimensional controllability of the bottom of the resist pattern, which leads to instability of the dimensions of the bottom of the etching pattern. means. Normally, the resist is baked to suppress such undulating shapes. As a result, the side walls of the resist pattern 5 have a smooth shape, and dimensional controllability is also greatly improved.

しかし、RIEのようなドライエツチングに際しては、
このなめらかなレジストパターン側壁において、エツチ
ング種であるイオンか反射し、被エツチング膜2のエツ
チング形状は第2図に示すようないびつな形状となる。
However, in dry etching such as RIE,
Ions, which are the etching species, are reflected from the smooth side walls of the resist pattern, and the etched film 2 has a distorted shape as shown in FIG.

即ち、半導体基板に垂直に入射するイオン4′は、レジ
ストパターン5の側壁において反射することなく入射し
、レジストパターンに忠実にエツチングを進行させる。
That is, the ions 4' that are perpendicularly incident on the semiconductor substrate are incident on the side walls of the resist pattern 5 without being reflected, and the etching progresses faithfully to the resist pattern.

しかし、半導体基板に対しである角度θて入射したイオ
ン4はレジストパターン5の側壁で反射した後、被エツ
チング膜2のエツチングを進行させる。これによって、
レジストパターン5下部の被エツチング膜2もエツチン
グされ、エツチング後の形状は第2図のようないびつな
形状となる。
However, the ions 4 incident on the semiconductor substrate at a certain angle θ are reflected by the side walls of the resist pattern 5, and then proceed to etch the film to be etched 2. by this,
The film to be etched 2 under the resist pattern 5 is also etched, and the shape after etching becomes a distorted shape as shown in FIG.

また第3図に示すように、従来のフォトレジスト5をマ
スクとしたエツチングでは、エツチングの進行とともに
フォトレジスト膜中5に入射したイオンによって電荷の
集中が生じ、基板上のフォトレジスト5がある領域付近
に局所的な電界6か発生する。この結果、基板へ入射す
るイオン4の方向がフォトレジスト5近傍に発生した電
界6によって曲げられるためにエツチング形状は歪んで
しまう。
Furthermore, as shown in FIG. 3, in conventional etching using the photoresist 5 as a mask, charge concentration occurs due to ions incident on the photoresist film 5 as etching progresses, and the area where the photoresist 5 is located on the substrate is concentrated. A local electric field 6 is generated nearby. As a result, the direction of the ions 4 incident on the substrate is bent by the electric field 6 generated near the photoresist 5, so that the etched shape is distorted.

このように従来例においては、半導体基板1に対しであ
る角度で入射するイオン4によるエツチング形状の劣化
は避けられず、特に微細なパターンのエツチングにおい
ては、デバイス精度を劣化させ、歩留りの低下や信頼性
の劣化を招き、大きな問題となっていた。
In this way, in the conventional example, deterioration of the etching shape due to the ions 4 incident on the semiconductor substrate 1 at a certain angle is unavoidable, and especially when etching a fine pattern, it deteriorates device precision, leading to a decrease in yield and This caused a major problem, leading to deterioration in reliability.

この発明は上記のような問題点を解決するためになされ
たもので、微細なパターンを高精度にエツチングでき、
歩留りの向上と、デバイスの信頼性向上を図ることがで
きる半導体集積回路装置の製造方法を提供することを目
的とする。
This invention was made to solve the above problems, and allows fine patterns to be etched with high precision.
An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can improve yield and device reliability.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体集積回路装置の製造方法は、多孔
質性金属膜をエツチングマスクとしてドライエツチング
により、被エツチング膜をエツチングするようにしたも
のである。
In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a film to be etched is etched by dry etching using a porous metal film as an etching mask.

〔作用〕[Effect]

本発明においては、被エツチング膜のドライエツチング
に際して、エツチングマスクとして多孔質性金属膜を用
いたのでエツチングマスクでのイオンの反射かなくなり
、マスクパターンに忠実にドライエツチングか行われ、
高精度な微細加工が可能となる。
In the present invention, since a porous metal film is used as an etching mask when dry etching a film to be etched, there is no reflection of ions from the etching mask, and dry etching can be performed faithfully to the mask pattern.
High-precision microfabrication becomes possible.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明による半導体集積回路装置の製造方法を
示す断面構造図である。図において、1は半導体基板、
2は被エツチング膜で、例えばSi酸化膜、Si窒化膜
、多結晶Si膜、或いはこれらの複数層から構成される
多層膜である。3は被エツチング膜のエツチングに際し
てエツチングマスクとなる多孔質性金属膜で、例えばT
i、TiN、 W、 WS i、 MoS i、 Ta
、 TaS i。
FIG. 1 is a cross-sectional structural diagram showing a method of manufacturing a semiconductor integrated circuit device according to the present invention. In the figure, 1 is a semiconductor substrate,
Reference numeral 2 denotes a film to be etched, which is, for example, a Si oxide film, a Si nitride film, a polycrystalline Si film, or a multilayer film composed of a plurality of these layers. 3 is a porous metal film that serves as an etching mask when etching the film to be etched; for example, T
i, TiN, W, WS i, MoS i, Ta
, TaSi.

TiW等の高融点金属或いはそれらの硅化物、もしくは
窒化物、または高融点金属間の化合物であって、例えば
スパッタリング法あるいはCVD法によって被エツチン
グ膜2上の全面に形成される。
It is a high melting point metal such as TiW, its silicide or nitride, or a compound between high melting point metals, and is formed on the entire surface of the film to be etched 2 by, for example, a sputtering method or a CVD method.

その後、通常の写真製版プロセスによって所望のレジス
トパターンを形成した後、RIEのようなドライエツチ
ングを行った後、レジストを除去することによって得る
。この時、多孔質性金属膜3の膜厚は、被エツチング膜
2をエツチングする際の選択比にも依るが、通常は20
00〜3000人程度以下の膜厚で十分である。また、
多孔質性金属膜3のエツチングに際して、フォトレジス
トをマスクに行うため、従来例の場合と同様にレジスト
側壁でのイオンの反射によるエツチング形状の劣化はあ
るか、多孔質性金属膜3の膜厚か2000〜3000人
と比較的薄いために大きな形状の劣化はなく、はぼフォ
トレジストパターン通りの所望のパターンを得ることか
できる。
Thereafter, a desired resist pattern is formed by a normal photolithography process, dry etching such as RIE is performed, and the resist is removed. At this time, the film thickness of the porous metal film 3 depends on the etching selectivity when etching the film to be etched 2, but is usually 20
A film thickness of about 0.00 to 3000 or less is sufficient. Also,
Since etching of the porous metal film 3 is performed using a photoresist as a mask, is there any deterioration of the etched shape due to reflection of ions on the side walls of the resist, as in the case of the conventional example, and the film thickness of the porous metal film 3? Since it is relatively thin (about 2,000 to 3,000 people), there is no major deterioration of the shape, and a desired pattern can be obtained just like the photoresist pattern.

このようにして形成した多孔質性金属膜3のパターンを
マスクとしてRIEを行い、被エツチング膜2のエツチ
ングを行う。この時、基板表面に対しである角度(θ)
を持って入射するイオン4は多孔質性金属膜の膜中へ入
射し、表面での反射は非常に小さい。従って、斜め方向
から入射するイオン4のエツチング形状に及はす悪影響
か少なくなり、高精度のエツチングか可能となる。
RIE is performed using the pattern of the porous metal film 3 thus formed as a mask, and the film to be etched 2 is etched. At this time, a certain angle (θ) with respect to the substrate surface
The ions 4 that enter the porous metal film with a . Therefore, the adverse effect of the ions 4 incident from an oblique direction on the etching shape is reduced, and highly accurate etching is possible.

また、エツチングマスク3が金属膜であることから従来
のフォトレジスト膜を用いる場合と違ってエツチングマ
スクの電荷の集中(チャージアップ)かないためにエツ
チングマスク中近傍での電界の発生はなく、その結果、
エツチング種であるイオンの方向性に及はす影響も小さ
く、基板に垂直に入射するイオンによってのみエツチン
グが進行するため、この点からも高精度の加工か可能と
なる。
Furthermore, since the etching mask 3 is a metal film, unlike when using a conventional photoresist film, there is no concentration of charge (charge-up) on the etching mask, so no electric field is generated near the middle of the etching mask. ,
The effect on the directionality of ions, which are the etching species, is small, and etching progresses only with ions that are incident perpendicularly to the substrate, so high-precision processing is also possible from this point of view.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、RJEのようなドライ
エツチングに際して、多孔質性金属膜をエツチングマス
クとして使用するようにしたので、マスクの側壁部での
イオンの反射か小さくなり、マスクパターンに忠実な高
精度なエツチングが可能となる効果がある。また、エツ
チングマスク中ての電荷の集中かなく、従って局所的な
電界の発生もないことから、主に基板に垂直に入射する
イオンによってのみエツチングか進行するために、高精
度なエツチングが可能であり、歩留りの向上及び高精度
で高信頼性の半導体集積回路装置の製造か可能となる効
果がある。
As described above, according to the present invention, since a porous metal film is used as an etching mask during dry etching such as RJE, the reflection of ions at the sidewalls of the mask is reduced, and the mask pattern is This has the effect of enabling faithful and highly accurate etching. In addition, since there is no concentration of charge in the etching mask and therefore no local electric field is generated, etching progresses only with ions that are incident perpendicularly to the substrate, making it possible to perform highly accurate etching. This has the effect of improving yield and making it possible to manufacture highly accurate and highly reliable semiconductor integrated circuit devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による半導体集積回路装置
の製造方法を示す断面図、第2図は従来例における半導
体集積回路装置の製造方法を示す断面図、第3図は従来
例の問題点を示す断面図である。 図において、1は半導体基板、2は被エツチング膜、3
は多孔質性金属膜、4は半導体基板に対して角度(θ)
で入射するイオン、4°は半導体基板に垂直に入射する
イオン、5はフォトレジストマスク、6は電界である。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing a semiconductor integrated circuit device in a conventional example, and FIG. 3 is a problem with the conventional example. It is a sectional view showing a point. In the figure, 1 is a semiconductor substrate, 2 is a film to be etched, and 3 is a semiconductor substrate.
is the porous metal film, 4 is the angle (θ) with respect to the semiconductor substrate
4° is the ion incident perpendicularly to the semiconductor substrate, 5 is the photoresist mask, and 6 is the electric field. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に素子を形成してなる半導体集積回
路装置の製造方法において、 多孔質性金属膜をマスクとしてドライエッチングを行い
、被エッチング膜のパターニングを行うことを特徴とす
る半導体集積回路装置の製造方法。
(1) A method for manufacturing a semiconductor integrated circuit device in which elements are formed on a semiconductor substrate, characterized in that dry etching is performed using a porous metal film as a mask, and the film to be etched is patterned. Method of manufacturing the device.
(2)上記多孔質性金属膜は、高融点金属膜、或いは高
融点金属膜の珪化物もしくは高融点金属膜の窒化物また
は高融点金属間化合物であることを特徴とする請求項1
記載の半導体集積回路装置の製造方法。
(2) Claim 1, wherein the porous metal film is a high melting point metal film, a silicide of a high melting point metal film, a nitride of a high melting point metal film, or a high melting point intermetallic compound.
A method of manufacturing the semiconductor integrated circuit device described above.
JP33583290A 1990-11-28 1990-11-28 Manufacture of semiconductor integrated circuit device Pending JPH04199514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33583290A JPH04199514A (en) 1990-11-28 1990-11-28 Manufacture of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33583290A JPH04199514A (en) 1990-11-28 1990-11-28 Manufacture of semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04199514A true JPH04199514A (en) 1992-07-20

Family

ID=18292906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33583290A Pending JPH04199514A (en) 1990-11-28 1990-11-28 Manufacture of semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04199514A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422312A (en) * 1994-06-06 1995-06-06 United Microelectronics Corp. Method for forming metal via
JP2009135475A (en) * 2007-10-31 2009-06-18 Mitsubishi Chemicals Corp Etching method and optical / electronic device manufacturing method using the same
CN110618179A (en) * 2019-09-23 2019-12-27 正仁(北京)医疗仪器有限公司 Glucose electrochemical microelectrode sensor based on nano porous metal film

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5422312A (en) * 1994-06-06 1995-06-06 United Microelectronics Corp. Method for forming metal via
JP2009135475A (en) * 2007-10-31 2009-06-18 Mitsubishi Chemicals Corp Etching method and optical / electronic device manufacturing method using the same
CN110618179A (en) * 2019-09-23 2019-12-27 正仁(北京)医疗仪器有限公司 Glucose electrochemical microelectrode sensor based on nano porous metal film

Similar Documents

Publication Publication Date Title
JP2002217170A (en) Method of forming fine pattern, method of manufacturing semiconductor device, and semiconductor device
US6235626B1 (en) Method of forming a gate electrode using an insulating film with an opening pattern
JPH05259467A (en) Method of forming a thin oxide portion, especially in an electrically erasable and writable read-only memory cell
US20010027027A1 (en) Ferroelectric random access memory device and method for manufacture thereof
JPS59126634A (en) Formation of pattern
JPH03278543A (en) Manufacture of field-effect transistor
JPS618952A (en) Forming method of wiring
JPH06224161A (en) Manufacture of semiconductor device
JPH03257825A (en) Manufacture of semiconductor device
JP2737256B2 (en) Method for manufacturing semiconductor device
JP2740292B2 (en) Method for manufacturing semiconductor device
JPS5950053B2 (en) Photo engraving method
JPS605230B2 (en) Manufacturing method of Josephson device
JPH08186115A (en) Method of forming metal film
JPS6195518A (en) Structure of alignment mark
JPS61114536A (en) Manufacture of semiconductor device
KR100278742B1 (en) Method of forming fine pattern of highly reflective material
JPS6196735A (en) Conductor pattern forming process
JPS63271957A (en) Formation of multilayer interconnection
JPS61296722A (en) Manufacture of semiconductor device
JPS59161024A (en) Formation of positioning mark
JP2000012528A (en) Etching method of film covering step
JPH03191575A (en) Formation of schottky junction electrode
JPS62235756A (en) Manufacture of semiconductor device
JPS59161026A (en) Etching