JPH04199531A - Measuring device for semiconductor - Google Patents

Measuring device for semiconductor

Info

Publication number
JPH04199531A
JPH04199531A JP2335383A JP33538390A JPH04199531A JP H04199531 A JPH04199531 A JP H04199531A JP 2335383 A JP2335383 A JP 2335383A JP 33538390 A JP33538390 A JP 33538390A JP H04199531 A JPH04199531 A JP H04199531A
Authority
JP
Japan
Prior art keywords
socket
tray
aging
cavities
cover
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2335383A
Other languages
Japanese (ja)
Inventor
Masaki Kinoshita
木下 雅喜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2335383A priority Critical patent/JPH04199531A/en
Publication of JPH04199531A publication Critical patent/JPH04199531A/en
Pending legal-status Critical Current

Links

Landscapes

  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To shorten time needed for inserting or extracting numerous ICs into or from an aging board, by making an IC receiving tray have IC positioning guides, measuring cavities, and cover pressing cavities. CONSTITUTION:An IC 5 to be measured, put on an IC receiving tray 1, is positioned with precision by the action of IC guides 7 on the tray 1, and fitted to an aging board 3 along with the tray 1. At this time, positioning of a socket 2 against the tray 1 is done with precision by socket positioning pins 13 and socket positioning holes 14, and contact pins 6 touch the IC leads 8 through cavities 11 for the contact pins. Next an IC socket cover 4 is fixed by inserting cover holdfasts 10 into cavities 12 for the cover holdfasts, and IC lead pressing protrusions 9 make the contact between the contact pins 6 and IC leads 8 secure. Accordingly, ICs received by the IC receiving tray can be inserted into or extracted from the aging board at one time, and the inserting or extracting time can be shortened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体集積回路(以下ICと呼ぶ)の高温エ
ージング試験に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to high temperature aging testing of semiconductor integrated circuits (hereinafter referred to as ICs).

〔従来の技術〕[Conventional technology]

近年ICの高集積化が進み、信頼性レベル向上の為高温
エージング試験を実施するものが増えてきている。
In recent years, as ICs have become more highly integrated, an increasing number of ICs are being subjected to high-temperature aging tests in order to improve their reliability.

第2図は従来のエージング基板の平面図、第3図は従来
のICソケットの正面図、第4図は従来のICトレイの
斜視図である。
FIG. 2 is a plan view of a conventional aging board, FIG. 3 is a front view of a conventional IC socket, and FIG. 4 is a perspective view of a conventional IC tray.

図において、(1)はIC収納トレイ、(2)はICC
エージノブソケット(3)はエージング基板、(4)は
ICソケット蓋、(6)は接触ピン、(7)はICガイ
ド、頭は蓋押えである。
In the figure, (1) is the IC storage tray, (2) is the ICC
The age knob socket (3) is an aging board, (4) is an IC socket lid, (6) is a contact pin, (7) is an IC guide, and the head is a lid holder.

次に動作について説明する。IC収納トレイ(1)から
測定IC(図示せず)を取り出し、ICガイド(7)に
沿ってICエージング用ソケット(2)に挿入する。次
にICソケット蓋(4)を閉じ蓋押え(101で固定す
る。
Next, the operation will be explained. A measurement IC (not shown) is taken out from the IC storage tray (1) and inserted into the IC aging socket (2) along the IC guide (7). Next, close the IC socket lid (4) and secure it with the lid holder (101).

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の半導体測定装置は以上の様に構成されていたので
、エージングを行う場合、IC1個についてエージング
用基板を必要とする為、多数のICを高温エージングす
る場合、人手、時間がかかるという問題点があった。
Conventional semiconductor measurement equipment was configured as described above, so when aging is performed, an aging substrate is required for each IC, so aging many ICs at high temperatures requires a lot of manpower and time. was there.

この発明は上記の様な問題点を解消する為になされたも
ので、ICをIC収納用トレイからICソケットへの移
し換えを無くした半導体測定装置を得ることを目的とす
る。
The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor measuring device that eliminates the need to transfer an IC from an IC storage tray to an IC socket.

[課題を解決するための手段] この発明に係る半導体測定装置は、IC収納)・レイに
IC位置決め用ガイド、測定用空洞、蓋押え用空洞を設
け、ソケットと一体化を可能としたものである。
[Means for Solving the Problems] A semiconductor measuring device according to the present invention is capable of integrating with a socket by providing an IC positioning guide, a measurement cavity, and a lid holding cavity in an IC housing/ray. be.

〔作用〕[Effect]

この発明における半導体測定装置は、トレイの材質を耐
熱性にする事によって、トレイこと高温エージングを実
施できる。
The semiconductor measuring device according to the present invention can perform high-temperature aging by making the material of the tray heat-resistant.

〔実施例〕〔Example〕

以下、この発明の装置実施例を図について説明する。 Hereinafter, embodiments of the device of the present invention will be described with reference to the drawings.

第1図はこの発明の一実施例である半導体測定装置の展
開斜視図で、図において、(1)はIC収納トレイ、(
2)はICエージング用ソケッl−、(31はエージン
グ用基板、(4jはICソケット蓋、(5)は被測定I
 C、filは接触ピノ、(7)はICガイド、(8)
はICリード、(9)はICリード押え、QOI +、
t M押え、(11)は接触ピノ用空洞、(12)は蓋
押え用空洞、(13)はソケット位置決めピン、(14
)はソケット位置決め用穴である。
FIG. 1 is an exploded perspective view of a semiconductor measuring device that is an embodiment of the present invention. In the figure, (1) is an IC storage tray;
2) is the IC aging socket l-, (31 is the aging board, (4j is the IC socket lid, and (5) is the measured I
C, fil is contact pinot, (7) is IC guide, (8)
is IC lead, (9) is IC lead holder, QOI +,
t M presser, (11) is a cavity for contact pinot, (12) is a cavity for lid presser, (13) is a socket positioning pin, (14)
) is the socket positioning hole.

次に動作について説明する。Next, the operation will be explained.

IC収納トレイ(1)に収納されている被測定IC(5
)は、トレイ(1)上のICガイド(7)の作用により
位置精度が図られ、トレイ(1)のままエージング用基
板(3)に取付ける。この時、ソケット位置決めピン(
13)、ソケット位置決め穴(14)により、ソケット
(2)とトレイ(1)との位置精度を出す。また、接触
ピン用空洞(12)により接触ピン(6)とICリード
(8)が接触する。次に蓋押えG〔を蓋押え用空洞(1
1)に通す事により、ICソケットN(4)が固定され
、ICリード押え(9)により接触ピン(6)とICリ
ード(8)の接触を確実にする。
The IC under test (5) stored in the IC storage tray (1)
), positional accuracy is ensured by the action of the IC guide (7) on the tray (1), and the tray (1) is attached to the aging board (3) as it is. At this time, the socket positioning pin (
13) The socket positioning hole (14) provides positional accuracy between the socket (2) and the tray (1). Further, the contact pin (6) and the IC lead (8) come into contact with each other through the contact pin cavity (12). Next, attach the lid presser G [to the lid presser cavity (1
1), the IC socket N (4) is fixed, and the IC lead presser (9) ensures contact between the contact pin (6) and the IC lead (8).

なお、上記実施例ではエージング基板挿入時を示したが
、抜き取り時も同様の効果が得られる。
Note that although the above embodiment shows the case when the aging board is inserted, the same effect can be obtained when the aging board is removed.

QFPパッケージのICでも同様の効果を奏する。Similar effects can be achieved with QFP packaged ICs.

〔発明の効果〕〔Effect of the invention〕

以上のようにこの発明によれば、収納トレイことICを
エージングできる様にしたので、収納トレイの収納数を
一度にエージング基板に挿入、抜き取りが行なえ、挿脱
時間の短縮に効果がある。
As described above, according to the present invention, since the storage tray or IC can be aged, the number of storage trays stored in the storage tray can be inserted into and removed from the aging board at one time, which is effective in shortening the insertion/removal time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの本発明の一実施例であるIC1個分の半導
体測定装置の展開斜視図、第2図は従来のエージング基
板の平面図、第3図は従来のICエージング用ソケット
の正面図、第4図は従来のIC収納トレイの斜視図であ
る。 図において、(1)はIC収納トレイ、(2)はICエ
ージング用ソケット、(3)はエージング用基板、(4
)はICソケット蓋、(5)は被測定I C、(61は
接触ピン、(7)はICガイド、(8)はICリード、
(9)はrcリード押え、(101は蓋押え、(11)
は接触ピン用空洞、(12)は蓋押え用空洞、(18)
はソケット位置決めピン、(14)はソケット位置決め
用穴を示す。 なお、図中、同一符号は同一、または相当部分を示す。
Fig. 1 is an exploded perspective view of a semiconductor measuring device for one IC which is an embodiment of the present invention, Fig. 2 is a plan view of a conventional aging board, and Fig. 3 is a front view of a conventional IC aging socket. , FIG. 4 is a perspective view of a conventional IC storage tray. In the figure, (1) is an IC storage tray, (2) is an IC aging socket, (3) is an aging board, and (4) is an IC aging socket.
) is the IC socket cover, (5) is the IC to be measured, (61 is the contact pin, (7) is the IC guide, (8) is the IC lead,
(9) is the rc lead holder, (101 is the lid holder, (11)
is a cavity for the contact pin, (12) is a cavity for holding the lid, (18)
indicates a socket positioning pin, and (14) indicates a socket positioning hole. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路の高温エージング試験において、収納用
トレイごとにエージングを実施できることを特徴とする
半導体測定装置。
A semiconductor measuring device characterized by being capable of aging each storage tray in a high temperature aging test of semiconductor integrated circuits.
JP2335383A 1990-11-28 1990-11-28 Measuring device for semiconductor Pending JPH04199531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2335383A JPH04199531A (en) 1990-11-28 1990-11-28 Measuring device for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2335383A JPH04199531A (en) 1990-11-28 1990-11-28 Measuring device for semiconductor

Publications (1)

Publication Number Publication Date
JPH04199531A true JPH04199531A (en) 1992-07-20

Family

ID=18287934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2335383A Pending JPH04199531A (en) 1990-11-28 1990-11-28 Measuring device for semiconductor

Country Status (1)

Country Link
JP (1) JPH04199531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100722643B1 (en) * 1998-04-02 2007-05-28 가부시키가이샤 어드밴티스트 Integrated Circuit Tester
KR100810380B1 (en) * 1998-04-01 2008-03-07 가부시키가이샤 어드밴티스트 Integrated Circuit Tester

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100810380B1 (en) * 1998-04-01 2008-03-07 가부시키가이샤 어드밴티스트 Integrated Circuit Tester
KR100722643B1 (en) * 1998-04-02 2007-05-28 가부시키가이샤 어드밴티스트 Integrated Circuit Tester

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