JPH041995A - 1-bit memory circuit - Google Patents

Abstract

PURPOSE:To decrease the number of integrated circuits and to enhance the effect more as the number of memories is increased more by employing a shift register circuit especially. CONSTITUTION:The 1-bit memory circuit is provided with a counter circuit 101 operated at a frame pulse with a period as that of an input data and a clock with a period being n-times of the period and a comparator circuit 102 comparing an output of the counter circuit 101 with an address bit. An n-stage shift register circuit 104 holding the input data and a selector circuit 103 inserting the input data to a feedback loop of the shift register circuit 104 and the output of the comparator circuit 102 is connected to a control signal of the selector circuit 103. Thus, the configuration is attained with integrated circuits on market of comparatively less quantity and the effect is enhanced more as the memory quantity is increased more especially.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a 1-bit memory circuit in a digital data communication device, and particularly to a 1-bit memory circuit in a digital data communication device, and in particular, a memory circuit for writing 1-bit input data to a position specified by a plurality of address bits. The present invention relates to a 1-bit memory circuit.

[Conventional technology]

FIG. 3 is a block diagram showing an example of a conventional 1-bit memory circuit, and FIG. 4 is a timing chart showing the operation in FIG. 3.

The circuit of this example has address bit A in the decoder circuit 305.
The insertion of D converts the address bits that arrive as binary constants into physical memory locations. Then, the output of the counter circuit 301 for phase matching for inserting the input data DI into the memory circuits 302 to 304 and the output of the decoder circuit 305 are connected to the clock CK of the memory circuits 302 to 304 via AND gate circuits 306 to 308. By inserting the data into the memory, the data becomes rewritable, and the state in the memory can be changed depending on the input data DI.

[Problem to be solved by the invention]

In the conventional 1-bit memory circuit described above, the output of the counter circuit and the output of the decoder circuit must be outputted via an AND gate circuit, so it is impossible to share the clock between each memory circuit. There is. Therefore, when a circuit is constructed using commercially available integrated circuits, there is a drawback that the number of integrated circuits increases. That is,
In commercially available integrated circuits, memory circuits with independent clocks have a small number of memories per integrated circuit, which is not desirable in terms of hardware configuration.

[Means to solve the problem]

A 1-bit memory circuit of the present invention includes a plurality of 1-bit memory circuits that each write 1-bit input data to a position designated by a plurality of address bits, a frame pulse having the same period as the input data, and a frame pulse having the same period as the input data. A counter circuit that operates with a clock n times as large as , a comparator circuit that compares the output of this counter circuit with the address bit, an n-stage shift register circuit that stores the input data, and a feedback loop of this shift register circuit. A selector circuit for inserting input data is provided, and an output of the comparator circuit is connected to a control signal of the selector circuit.

[Effect]

The 1-bit memory circuit of the present invention is based on the principle that the shift register circuit returns to its original state by applying feedback and clocks for the number of register stages.When rewriting specific memory contents, the address bit is converted into a temporal phase signal. However, by inserting input data into the feedback loop of the shift register circuit, it has the same function as a conventional 1-bit memory circuit. Therefore, in shift register circuits, each register uses a common clock, and commercially available shift register integrated circuits have a large number of memories, so
It is possible to construct a structure using a relatively small number of integrated circuits.

〔Example〕

Next, the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing one embodiment of the 1-bit memory circuit of the present invention, and FIG. 2 is a timing chart showing the operation in FIG. 1.

In FIG. 1, the circuit configuration of this embodiment is as follows: input data D
A frame pulse FP with the same period as I, and n of this period
A counter circuit that operates with twice the clock CLK (hereinafter referred to as C
NT) 101, a comparator circuit R (hereinafter referred to as CMP) 102 that compares the outputs Q1 to Qm of the CNT 101 and address bits AD (A1-Am), and an n-stage shift register circuit (hereinafter referred to as 5HR) that stores input data DI. The CMP
The output Q of 5EL 102 is connected to terminal C of 5EL 103 as a control signal 115. 5EL103 is the input data DI to terminal A and the existing data 117 of the feedback loop to terminal B.
and outputs data 116 from terminal Y. Also, DO1~Do (n-1'), Don is 5HR104
This is the output data from.

FIG. 2 is an operation diagram that takes as an example the case where "1°" of input data DI is written to the 5th bit of memory. are compared by CMP 102, and the obtained control signal 115 is input to 5ELIO3 to control the selection between input data DI and existing data 117. Frame pulse FP is generated between address bits A1 to Am and input data DI.
is measuring the period of Terminal Y selected by 5EL103
The existing data 117 is the input data D.
This shows the timing of the change to I.

〔Effect of the invention〕

As explained above, by using a shift register circuit, the present invention has the effect of reducing the number of integrated circuits compared to the conventional 1-bit memory circuit configuration, and especially as the amount of memory increases. The effect is noticeable.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a 1-bit memory circuit of the present invention, FIG. 2 is a timing chart showing the operation in FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional 1-bit memory circuit. , FIG. 4 is a timing chart showing the operation in FIG. 3. 101... Counter circuit (CNT), 1.02...
Comparator circuit (CMP), 103... Selector circuit (SEL), 104... Shift register circuit (SH
R), 301... counter circuit, 302-304...
-Memory circuit, 305...Decoder circuit, 306-3
08...AND gate circuit.

Claims (1)

[Claims] In a 1-bit memory circuit that each writes 1-bit input data to a position specified by a plurality of address bits, a counter operates with a frame pulse having the same period as the input data and a clock n times the period. a comparator circuit that compares the output of this counter circuit with the address bit, an n-stage shift register circuit that stores the input data, and a selector circuit that inserts the input data into a feedback loop of the shift register circuit. A 1-bit memory circuit comprising: an output of the comparator circuit connected to a control signal of the selector circuit.