JPH0420014A - Reset circuit in PLL circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] "Industrial Application Field" The present invention provides a PLL circuit installed in a transmitter/receiver etc.
This invention relates to a reset circuit in a PLL circuit in which the CPU in the PLL circuit operates only when necessary.

"Prior art" When a transmitter, receiver, or transceiver is controlled by a PLL circuit, a CPU built in this PLL circuit
occurs when an abnormality occurs in the power supply voltage.

The reset circuit is activated to unlock the PLL circuit. Specifically, in FIG. 2, when a power supply voltage or a control signal corresponding thereto is inputted to the input terminal (1), and an abnormal voltage detection circuit at the time of an abnormal voltage is inputted to this input terminal (1).

Abnormal voltage detection circuit (7) consisting of transistor (2), Zener diode (3), resistor (4) (5) (6)
) turns on. Then, it is input to one side of the OR gate (10) via the inverters (8) and (9), and the inverter (11)-delay circuit (12) and the inverter (1
3) to the other side of the OR gate (10), and at the same time the signal of the standby output terminal (14) disappears, the reset terminal (1) is inputted via the inverter (15).
The reset signal 6) is output and the CPU is reset and returns to normal operation with the PLL circuit 11m disconnected.

[Problem to be solved by the invention] In the conventional circuit shown in Figure 2, the reset was performed only by the abnormal voltage detection signal, but with the advent of control using digital signals, the transmission that sends and receives weak radio waves has become necessary. In devices and receivers, there has been a problem in that signals with large voltages, such as digital signals, are output as noise.

SUMMARY OF THE INVENTION An object of the present invention is to obtain a circuit that eliminates noise factors caused by digital signals when unnecessary.

"Means for Solving the Problems" The present invention controls a controlled machine using a PLL circuit built into a CPU, and outputs a reset signal when an abnormal voltage detection signal from a power supply is input to unlock the PLL circuit and resume normal operation. In the reset circuit of the PLL circuit configured to return, the input terminal of the abnormal voltage detection signal is coupled to one input terminal of a gate circuit, and the input terminal of the PLL circuit is connected to the other input terminal of the gate circuit.
The lock detection signal output terminal of the LL circuit is coupled, and in addition to the abnormal voltage detection signal, this lock detection signal is also used as the C
This is to control the reset of the PU.

"Operation" When a controlled device such as a transmitter/receiver is controlled by a PLL circuit with a built-in CPU, if an abnormal voltage detection signal of the power supply and/or a lock detection signal of the PLL circuit is input to the gate circuit, a reset signal is generated. Output and PLL
The circuit is unlocked. Therefore, noise caused by digital signals is removed.

"Example" An embodiment of the present invention will be described below with reference to FIG.

In FIG. 1, (17) is the same conventional circuit as in FIG.
is inserted. That is, a gate circuit (19) consisting of a Nant gate of this additional circuit (18) is inserted between the inverters (9) and (11), and this gate circuit (19) is inserted between the inverters (9) and (11).
The abnormal voltage detection circuit (7) of the conventional circuit (17) is coupled to one input side of the circuit (9). In addition, the other two input sides of the gate circuit (19) include lock detection signal input terminals (20) for the PLL circuit for the transmitter and the PLL circuit for the receiver.
(21) and inverter (22) (23) respectively
, (24) and (25) are bonded by -C.

In such a configuration, input terminals (1) (20) (
21) When no signal is input to any of them, the CPUs of the PLL circuits in the transmitter and receiver operate, sending data to each PLL circuit and locking it. Then, the CPU enters standby mode by a signal from the standby output terminal (14).

Next, when a signal is input to at least one of the power supply voltage abnormality input terminal (1), the transmitter's lock detection signal input terminal (20), and the receiver's lock detection signal input terminal (21), An output is obtained from the gate circuit (19). This output is input to one side of the OR gate (1,0), and is also input to the other side of the OR gate (10) via an inverter (11), a delay circuit (12), and an inverter (13), and is input to the standby output. There is no output from terminal (14). At the same time, a reset signal is output from the reset output terminal (16) via the inverter (15), the CPU of each transceiver is reset, and the PLL circuit returns to normal operation with the lock released. In this way, in addition to the abnormal voltage detection signal, the lock detection signal of the PLL circuit also
PU reset is controlled.

``Effects of the Invention'' Since the present invention is configured as described above, when the controlled device is a transmitter/receiver that transmits and receives radio waves with a weak electric field, it can be used not only when the power supply voltage is abnormal, but also when a large voltage signal such as a digital signal is generated. etc., can block input when unnecessary and remove noise factors.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing a first embodiment of a reset circuit in a PLL circuit according to the present invention, and FIG. 2 is an electric circuit diagram of a conventional circuit. (1)...Input terminal, (2)...Transistor, (
3)...Zener diode, (4) (5) (6)
...Resistance, (7) ...Abnormal voltage detection circuit, (8)
(9) (11) (13) (15) (22) (2
3) (24) (25)...Inverter, (10)
...OR gate, (12) ...Delay circuit, (14)
... Standby output terminal, (16) ... Reset output terminal, (17) ... Conventional circuit, (18) ... Additional circuit. (19)...Gate circuit, (20) (21)...
Lock detection signal input terminal. Applicant Fujitsu General Ltd.

Claims (1)

[Claims] (1) A PLL circuit reset circuit that controls the controlled machine with a PLL circuit built into the CPU, and outputs a reset signal when an abnormal voltage detection signal from the power supply is input to unlock the PLL circuit and return to normal operation. , the input terminal of the abnormal voltage detection signal is coupled to one input terminal of a gate circuit, and the input terminal of the PL is connected to the other input terminal of the gate circuit.
The lock detection signal output terminal of the L circuit is coupled, and in addition to the abnormal voltage detection signal, this lock detection signal is also used to output the CP.
P characterized in that the reset of U is controlled.
Reset circuit in LL circuit.