JPH0420071A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an image processing device that performs pixel density conversion.

[Prior Art] Conventionally, for example, in a facsimile machine, when converting the resolution of a received image or recording input low print density data with a high print density LBP, etc., pixel density conversion of a binary image is performed. There is. In particular, when performing pixel density conversion from low pixel density to high pixel density, it is necessary to take advantage of the high pixel density (jaggies between black areas such as diagonal lines and white areas (jaggies in pixel units caused by diagonal lines, etc.) ), interpolation processing is performed with the aim of solving this problem.

Furthermore, in order to express intermediate color images such as photographs using binary data, dither processing is used as a binarization method, for example. In dither processing, a larger area as shown in FIG. 7(a) is virtually set for the unit pixel shown in FIG. 7(b), and multivalued data is divided into that area using a predetermined dither matrix. Halftone expression is performed by converting the black/white pixel number ratio of the unit pixel within. The area for expressing this halftone is hereinafter referred to as a unit, and the number of units included in a certain length is the number of screen lines, and the size (width) of that unit is the resolution of the halftone image. .

[Problems to be Solved by the Invention] However, in the conventional example described above, as is clear from the size of the unit shown in FIG. 7(a), the resolution of the halftone image is inferior to the resolution of the binary image. In conventional interpolation processing, the resolution in halftone representation of a binary image was not improved despite the increase in pixel density, and the benefits of higher pixel density were not achieved.

The present invention was made to solve the above problems, and
When converting pixel density, by installing a circuit that detects the size of the unit that expresses halftones and divides the detected unit as the resolution increases, the number of screen lines can be increased and the image quality can be improved. The purpose is to provide an image processing device that can be improved.

[Means for Solving the Problems] In order to achieve the above object, an image processing device of the present invention has the following configuration. That is, a receiving means for receiving dot information of a first recording dot density, a storage means for storing the dot information from the receiving means, and a second recording dot density based on the dot information stored in the storage means. In an image processing apparatus, the image processing apparatus includes a generating means for generating density dot information, and a detecting means for detecting a screen line number for specifying the resolution of an image included in the first dot information, and increasing the screen line number from the detecting means. and an output means for outputting halftone image information converted by the converting means.

[Operation] In the above configuration, the number of screen lines that specifies the resolution of the halftone image included in the first dot information is detected, the detected number of screen lines is increased to convert the resolution, and image processing is performed. , outputs halftone image information.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In this embodiment, a case where the unit width (screen line number) is detected in the main scanning direction and the units are divided in the main scanning direction will be described as an example.

FIG. 1 is a configuration diagram of a pixel density conversion circuit in this embodiment. In the figure, numeral numeral numeral numeral 1 indicates a period extraction circuit that detects the unit width, 2 a frequency division circuit, and 3 a unit division circuit. In this embodiment, the circuit converts the pixel density to twice the pixel density in the scanning direction. be.

301 and 302 are FIFOs for storing image data.
It is a buffer and stores first dot information VDO 405 sent from a host computer etc. in synchronization with VCLK 401. 402 is a beam detect signal (BD
), which is a synchronization signal for line sequential scanning. Figure 3(a)
A VDO signal obtained by scanning a halftone expression such as the one shown in FIG. 4 has a waveform consisting of a series of pulses as shown in FIG. Since the pulse width becomes thicker or thinner due to changes in the gradation expression of the unit, it fluctuates wildly at the rise or fall of the pulse, making it impossible to extract a stable period. However, since the pulse center does not change, the unit width is determined by counting the period of the pulse center using the pixel clock.

The period extraction circuit 1 inputs the BD and VCLK, and outputs the unit width to the frequency division circuit 2 as a binary output.

Frequency divider circuit 2 divides the clock twice as much as VCLK, and
Signal 4 in which 50% is rHJ and 50% is rLJ in the time it takes for D to scan the pixels of the unit width in FIG. 3(a).
Outputs 03. The signal 403 is input to the unit division circuit 3.

The FIFOs 301 and 302 of the unit dividing circuit 3 are alternately selected by the signal 403 from the frequency dividing circuit 2, and during the selected period, the VDO signal is output to the FIFOs 301 and 30.
2 to VCLK at twice the frequency. As a result, as shown in FIG. 3(b), a pattern is obtained in which two units of the same shape each having a width of 1/2 are lined up. The number of units has been doubled in the scanning direction, and density information (black/white pixel number ratio) is maintained.

Note that in this embodiment, the division is 2, but the FIFO
Increase the number of buffers and use a clock that is an integral multiple of VCLK.
By supplying the data to the IFO and adding a selection circuit, arbitrary division into n is possible.

Next, the inside of the above-mentioned period extraction circuit 1 will be described in detail with reference to the block diagram shown in FIG.

501 is a pixel number counter ('[1otCount) that counts -VCLK401. 502 is VDO4
This is a latch that holds the number of pixels Tr at the rising edge of 05. 503 is an adder that outputs the sum of the pixel value Tr at the time of rising and the current value.

Since the frequency dividing circuit 2 takes in data at the falling edge of the VDO 405, if the least significant bit is ignored, the output value will be an intermediate value between the rising edge and the falling edge, that is, the pulse center value T1.

Subtractor 50 subtracts the previous value T m-+ from this number of pixels T.
The signal 406 subtracted by 5 indicates the number of pixels between pulse centers, which is the unit width T. Further, the adder 506 adds the unit [
T= is added, and the result is held in latch 504 as the value of T, in preparation for the next operation. In this circuit, when the number of black (ON) pixels of the VDO 405 is odd and asymmetrical, the value of T may shift. Here, the least significant bit is discarded, so even if the rise is delayed, T
, does not change, but if the fall occurs earlier, T becomes shorter, so normal division is not performed.

However, since the data is held in FIFOs 301 and 302, data will not be lost even if the division is disrupted, and the density information (white/black pixel number ratio) and its position will be stored inside the unit before division of the original image data. is maintained. Therefore, in Figure 2, where the average unit width is not calculated (when the detected unit width is used to divide the next unit), it will not actually look like Figure 3 (b), The result will be as shown in FIG. 3(d). For this purpose, a circuit for calculating an average value may be inserted in 406 depending on the case.

Next, the frequency dividing circuit 2 in this embodiment will be explained below with reference to the block diagram shown in FIG.

In the figure, 201 is a down counter that divides the frequency of x2VcLK404. 202 is a latch that holds the value 406 from the period extraction circuit 1;

Then, the value of the latch 202 is shifted by 1 bit to the counter 201, and inputted as a double value.
The least significant input bit of 1 is fixed at "0". 20
8 is a latch that holds the output of the latch 202 at the same time as the counter 201, but the value input to the latch 202 is not shifted.@204 is a latch that sets the maximum length of the period to be detected. Comparison circuits 203 and 205 compare the magnitudes of the two inputs A and B.

This frequency dividing circuit 2 counts down the number of pulses of the x2VcLK404, and when it matches the value held in the latch 208, that is, when it becomes 1/2 of the initial value, it starts the flip-flop (RS-FF) 210. Let it set.

Furthermore, when the countdown continues and all the outputs become "0", the output of the OR gate 209 becomes zero. At this time, the counter 201 and the latch 208 include the latch 202
The output of is reloaded.

In addition, the line-sequentially scanned output does not have periodicity like T depending on the area. For this purpose, signal 406 (T
w) is compared with the value of the latch 204, and when the period exceeds a certain value, it is determined that there is no correlation. And x2V
CL obtained by dividing cLK404 with flip-flop 206
K is selected by data select 207, and unit division circuit 3 is bypassed.

In this example, processing is performed only in the horizontal direction, but
If the same type of processing is performed in the vertical direction using a frame memory, the pattern shown in FIG. 3(a) can be converted to the pattern shown in FIG. 3(C).

[Other Embodiment 1] In the above-described embodiment, since division is performed in both horizontal and vertical directions, a frame memory is required, which increases cost. Therefore, as another embodiment, a circuit example will be shown in which the number of lines in the vertical direction is increased without using a frame memory. FIG. 6 shows an outline of another embodiment.

In this circuit, the image period is set to T, which is always constant. Therefore, the advantage of this circuit is that the image can be reliably divided into units of constant size and no disturbances will occur. However, on the other hand, there is no followability.

The circuit also includes Kn line buffers 610 and 62.
Consists of 0. Here, K is the number of cell divisions in the vertical direction. The following description will be made assuming K=2.

From these 2n line buffers to register T.

Line buffers with a period set to 690 are selected. Line buffers 610 and 620 are divided into two sets, and while data is being written to one, data is being read from the other.

In order to match the read timing and write timing, the data read clock is twice the write clock.

At the time of writing, the counter 601 or 602 is incremented by a synchronizing signal WBD for line sequential scanning of data writing. Its output is the decoder 603
or 604, and line buffers 610 or 620 are sequentially selected. Then, data is written to the line buffer 610 or 620 in synchronization with WCLK. In addition, the WBD count output is from the comparator 6.
05 or 606, and if they match, the counter 601 or 602 is reset by the output of the comparator 605 or 606. As a result, the flip-flop 691 is inverted, and the two sets of line buffers 6
10,620 will be exchanged. Switching between reading and writing is performed by data selectors 607 and 608.

The written data is then transferred to the buffer 610 or 62 by RBD of the line sequential scanning synchronization signal with twice the frequency.
0 is selected and read by RCLK at twice the frequency of WCLK.

Address counters 630 and 631 are reset each time a synchronization signal is input.

Furthermore, when the count output of RBD matches T, the counter 601 or 602 is reset, so the same data will be read twice. However, when writing, the matching output is masked and does not affect the flip-flop.

Since a line buffer is used in this circuit, the value of T is fixed, and T, which is detected by horizontal scanning, is
Use the value of .

By performing the process of this example after performing the process of the previous example, the number of units per inch in both the horizontal and vertical directions as shown in FIG. Image data with an improved screen line count can be obtained.

[Effects of the Invention] As explained above, according to the present invention, when converting the pixel density, by providing a circuit that detects and divides the unit period expressing halftones in units of scanning lines, the screen The number of lines can be increased and the image quality can be improved.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the general configuration of the device in the example, Figure 2 is a diagram showing the configuration of the frequency extraction circuit, and Figure 3 (a).
-(d) are diagrams showing input image patterns, Figure 4 is a time chart showing line-sequentially scanned image signals and their timing, Figure 5 is a diagram showing the configuration of the frequency dividing circuit, and Figure 6 is the main A diagram showing another embodiment of the invention, FIG. 7(a)
) is a diagram showing a unit, and FIG. 7(b) is a diagram showing a unit pixel. In the figure, 1... frequency extraction circuit, 2... frequency dividing circuit, 3
...Image division circuit, 301, 302...FIFO buffer, 303,207,607,608...Data selector, 401...VCLK, 402...Scanning line switching synchronization signal, 403...Buffer Selection signal, 404
...X2VCLK. O (b) Fig. 7

Claims (1)

[Scope of Claims] Receiving means for receiving dot information of a first recording dot density; storage means for storing dot information from the receiving means; 2
an image processing device comprising a generating means for generating dot information with a recording dot density of An image processing apparatus comprising: a converter for converting the resolution of halftone expression by increasing the number of pixels; and an output means for outputting halftone image information converted by the converter.