JPH0420144U - - Google Patents
Info
- Publication number
- JPH0420144U JPH0420144U JP6105290U JP6105290U JPH0420144U JP H0420144 U JPH0420144 U JP H0420144U JP 6105290 U JP6105290 U JP 6105290U JP 6105290 U JP6105290 U JP 6105290U JP H0420144 U JPH0420144 U JP H0420144U
- Authority
- JP
- Japan
- Prior art keywords
- debugger
- system bus
- modules
- instructions
- information processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims description 4
- 238000012423 maintenance Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Multi Processors (AREA)
Description
第１図はこの考案の一実施例による情報処理装
置を示すブロツク図、第２図および第３図は従来
の情報処理装置を示すブロツク図である。
１０は情報処理装置、１１はモジユール（基板
実装形コンピユータ）、１２はモジユール（シス
テムメモリ）、２５はデバツガインタフエース、
３０はシステムバス、４０，４００は内部バス、
５０はデバツガ。なお、図中、同一符号は同一、
または相当部分を示す。
FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of this invention, and FIGS. 2 and 3 are block diagrams showing conventional information processing apparatuses. 10 is an information processing device, 11 is a module (board mounted computer), 12 is a module (system memory), 25 is a debugger interface,
30 is a system bus, 40,400 is an internal bus,
50 is Debatsuga. In addition, in the figure, the same reference numerals are the same,
or a significant portion.
Claims (1)
れた複数のモジユールと、該モジユールにおける
メモリ内容のトレースの命令をデバツガインタフ
エースを介して受け、この命令を実行してメンテ
ナンスを行うデバツガとを備えた情報処理装置に
おいて、上記デバツガを、上記デバツガインタフ
エースを介してシステムバスに直接接続したこと
を特徴とする情報処理装置。 The system includes a plurality of modules whose internal buses are connected via a common system bus, and a debugger that receives instructions for tracing memory contents in the modules via a debugger interface and executes the instructions for maintenance. An information processing apparatus characterized in that the debugger is directly connected to a system bus via the debugger interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6105290U JPH0420144U (en) | 1990-06-08 | 1990-06-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6105290U JPH0420144U (en) | 1990-06-08 | 1990-06-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420144U true JPH0420144U (en) | 1992-02-20 |
Family
ID=31588960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6105290U Pending JPH0420144U (en) | 1990-06-08 | 1990-06-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420144U (en) |
-
1990
- 1990-06-08 JP JP6105290U patent/JPH0420144U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0927938A4 (en) | Data transfer method and device | |
| JPS59108942U (en) | Computer system self-diagnosis device | |
| JPS61172346U (en) | ||
| JPS6368054U (en) | ||
| JPS635542U (en) | ||
| JPH0218167U (en) | ||
| JPS61272861A (en) | Multiprocessor device | |
| JPH02149444U (en) | ||
| JPS60164254U (en) | data transfer device | |
| JPS58147050U (en) | information processing equipment | |
| JPS60180066U (en) | Image processing device | |
| JPS6384650U (en) | ||
| JPS6339757U (en) | ||
| JPS62166558U (en) | ||
| JPS63136449U (en) | ||
| JPS62199869U (en) | ||
| JPH0242141U (en) | ||
| JPH0444790U (en) | ||
| JPH02126239U (en) | ||
| JPS59107800U (en) | Computer system function check device | |
| JPS6151548U (en) | ||
| JPS6312234U (en) | ||
| JPH026353U (en) | ||
| JPS6034647U (en) | microprocessor | |
| JPH0466625U (en) |