JPH0420163U - - Google Patents
Info
- Publication number
- JPH0420163U JPH0420163U JP6001290U JP6001290U JPH0420163U JP H0420163 U JPH0420163 U JP H0420163U JP 6001290 U JP6001290 U JP 6001290U JP 6001290 U JP6001290 U JP 6001290U JP H0420163 U JPH0420163 U JP H0420163U
- Authority
- JP
- Japan
- Prior art keywords
- circuit diagram
- editor
- lsi design
- logic simulator
- design device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 claims description 13
- 238000004088 simulation Methods 0.000 claims description 3
- 238000005070 sampling Methods 0.000 claims 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の一実施例を示すブロツク構成
図。第２図はその動作を示す流れ図。第３図はそ
の表示例１を示す説明図。第４図はその表示例２
の要部を示す説明図。第５図はシミユレーシヨン
モデルを示す回路図。第６図はシミユレーシヨン
パターンを示す説明図。第７図は従来例を示すブ
ロツク構成図。第８図はその表示例を示す説明図
。
１……モニタ画面、２，３，５……表示領域、
４……コマンド入力領域、６……アンドゲート、
７……ノアゲート、１０……ＬＳＩ設計装置、１
１……回路図エデイタ、１２……論理シミユレー
タ、１２ａ……状態表示手段、Ａ，Ｂ，Ｃ……入
力信号、Ｄ……出力信号、Ｎ１……ネツト。
FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a flowchart showing the operation. FIG. 3 is an explanatory diagram showing display example 1. Figure 4 shows example 2 of the display.
An explanatory diagram showing the main parts of. FIG. 5 is a circuit diagram showing a simulation model. FIG. 6 is an explanatory diagram showing a simulation pattern. FIG. 7 is a block diagram showing a conventional example. FIG. 8 is an explanatory diagram showing an example of the display. 1... Monitor screen, 2, 3, 5... Display area,
4...Command input area, 6...And gate,
7... Noah Gate, 10... LSI design equipment, 1
1...Circuit diagram editor, 12...Logic simulator, 12a...Status display means, A, B, C...Input signal, D...Output signal, N1...Net.
Claims (1)
る手段を含む論理シミユレータと を備えたＬＳＩ設計装置において、 前記論理シミユレータは、任意のサンプル時点
におけるシミユレーシヨンの実行結果を前記回路
図エデイタで作成した回路図上に直接表示する状
態表示手段を含む ことを特徴とするＬＳＩ設計装置。[Claims for Utility Model Registration] In an LSI design device comprising a circuit diagram editor and a logic simulator including means for displaying a circuit diagram created by the circuit diagram editor, the logic simulator is configured to perform simulation at an arbitrary sampling point. 1. An LSI design device comprising: status display means for directly displaying the execution result on a circuit diagram created by the circuit diagram editor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001290U JPH0420163U (en) | 1990-06-05 | 1990-06-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001290U JPH0420163U (en) | 1990-06-05 | 1990-06-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420163U true JPH0420163U (en) | 1992-02-20 |
Family
ID=31587016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6001290U Pending JPH0420163U (en) | 1990-06-05 | 1990-06-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420163U (en) |
-
1990
- 1990-06-05 JP JP6001290U patent/JPH0420163U/ja active Pending
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