JPH042018B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transistor circuit, and more particularly to a pilot tone type FM multiplex demodulation circuit.

An example of the configuration of this type of FM multiplex demodulation circuit integrated into an integrated circuit is shown in FIG. In FIG. 1, an FM composite signal 1 enters an input terminal 3 of an integrated circuit 2 and is guided to a phase comparator 5 forming a phase locked loop (PL) with a demodulator 4. A low pass filter (L・P・F) 6 is disposed at the output of the phase comparator (PD) 5, and removes high frequency components included in the output of the phase comparator 5 to generate a voltage controlled oscillator (V・C・O)
Controls the oscillation frequency of 7. Usually the pilot
The pilot frequency of the tone method is 19KHz,
Since VCO 7 is oscillating at 76KHz, which is 4 times higher, the first frequency divider 8 changes the frequency to 38KHz, and the second frequency divider 9 changes the frequency to 38KHz.
The frequency is divided into 19 KHz, and this 19 KHz is used as the comparison frequency of the phase comparator 5 to configure P, L, and L. On the other hand, the 38KHz signal frequency-divided by the first frequency divider 8 is used as the switching frequency of the demodulator 4, and the output terminals 10 and 11 are connected to load resistors 12 and 13.
De-emphasis capacitors 14 and 15 are connected to obtain stereo demodulated outputs of right and left channel components.

Normally, it is the demodulator 4 that prevents low voltage operation of the FM multiplex demodulator circuit, and low voltage operation of the local circuit block is becoming easily realized. This will be explained with reference to FIG.

FIG. 2 shows a conventional example of the demodulator 4, in which transistors 20, 21, 22, and 23 are double-balanced differentially connected, and resistors 24 and 25 are connected between each common base and a power supply terminal 200. Resistors 26 and 27 and transistors 28 and 2 are connected to ground 100, respectively.
9 connected in series, transistor 2
8 and 29 are injected with 38 KHz switching signals which are the outputs of the first frequency divider 8 and are in opposite phases to each other. A transistor 3 is connected to the common emitter of each of the transistors 20 and 21, 22 and 23.
A common emitter circuit consisting of resistors 32 and 33 is connected, and the base of the transistor 31 is connected to a bias source 3 having the same potential as the base of the transistor 30.
Connect to 4. On the other hand, the base of the transistor 30 is connected to a diode 35, transistors 36, 37,
A constant voltage circuit 41 consisting of a resistor 38 and constant current sources 39 and 40 includes resistors 42 and 43 and a transistor 4.
4, 45, 46, and an input power supply circuit 48 consisting of a constant current source 47 is connected to the transistor 4.
The emitter of transistor 5 and the collector of transistor 46 are connected to a connection point. The aforementioned transistor 2
The collectors of transistors 49 and 5 are connected to the collectors of transistors 49 and 5.
0 is connected, and the collector of the transistor 50 is connected to the demodulator output terminal 10.
A de-emphasis load circuit consisting of a resistor 12 and a capacitor 14 is connected. Similarly, a current mirror circuit of transistors 51 and 52 is connected to the collectors of the transistors 21 and 23, and the collector of the transistor 52 becomes the demodulator output terminal 11, where a resistor 13 and a capacitor 1 are connected.
A de-emphasis circuit consisting of 5 is connected. The base of the transistor 44 becomes the input terminal 3, into which the composite signal 1 is introduced via the capacitor 16.

A demodulator that requires low voltage operation must satisfy the following equation.

Vcc≧V _R32 +V _CE (sat) _Q30 +V _CE (sat) _Q20 +V _BEQ49 … V _R24OR25 +V _BEQ20 ≧V _CE sat _Q20 +V _BEQ49 … Here, Vcc is the power supply voltage, V _R (n) is the resistance _R
(n) voltage drop, V _CE (sat) Q(n) is the collector-emitter saturation voltage of transistor n, V _BEQ
(n) is the base-emitter voltage of transistor n.

Considering low voltage operation with Vcc = 3v and up to standard 1.8v operation, the input signal is 300mvrms, the voltage gain of the demodulator is odB, and the output day emphasis during FM demodulation is a time constant of 50μsec.
Furthermore, the capacitor 12 of the output terminals 10 and 11,
Based on the constraint of 13, if the capacitor is 0.15μF, which is easy to take with the _E6 series, the load resistance is uniquely 12,
The value of 13 is fixed around 3.3kΩ. On the other hand, by setting the voltage gain of the demodulator to odB, transistor 3
If the emitter area ratio of the current mirror circuits 49 and 50, 51 and 52 is 1:1, the value of the emitter resistors 32 and 33 of 0 and 31 is 1/2 of the load resistance, and R ₃₂ = R ₃₃ ≒ _3.3 kΩ/ ₂ . Also, the emitter grounded transistors of transistors 30 and 31 have an input signal level of 300mvrms (=424mvpeak).
In order to amplify the voltage without distortion, the drop voltage _VR32 of the resistor _R32 must be _VR32 ≧424mv. In the formula, generally speaking, transistors have V _BE ≒0.7v and V _CE sat≒0.2, so by substituting the typical values into the formula, Vcc≧V _R32 +V _CE (sat) _Q30 +V _CE + (sat ) ₂₀ +V _BEQ47 =0.424+0.2+0.2+0.7 =1.52(v). In other words, Vcc≧1.8v or more is satisfied, but in the formula, V _BEQ20 V _BEQ49 , and the resistance 2
The voltage drop in transistors 4 and 25 is due to the base current of transistors 20, 21, 22, and 23 flowing through this resistor, so V _{R24 = R25} < V _CE sat _Q20 , which does not satisfy. As a result, as shown in Figure 3, even at low input signal levels, the transistor 2
Since transistors 0 to 23 are operating in the saturation region, distortion cannot be maintained, and at high input signal levels, the saturation voltage between the collectors and emitters of transistors 20 to 23 becomes even larger, resulting in worsening of distortion. Ta.

An object of the present invention is to provide a transistor circuit that enables low voltage operation and is suitable for a stereo demodulation circuit.

The present invention is characterized by an expanded dynamic range in the signal supply to the dual Heihei differential amplifier.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 4 shows an embodiment of the present invention, and the same parts as in FIG. 2 are designated by the same reference numerals and the explanation thereof will be omitted. The difference from the conventional example is that constant current sources 53 and 54 are provided between each of the resistors 25 and 24 and the ground terminal 100, and each is composed of a transistor 55, a resistor 57, a transistor 56, and a resistor 58. Ru. Constant current sources 53 and 54 are Io ₅₃ and Io _54, respectively.
A constant current of . Therefore, the voltage drops V _R24 ′ and V _R25 ′ across the resistors 24 and 25 are expressed as VR ₂₄ ′=R ₂₄ ×Io ₅₃ , … VR ₂₅ ′=R ₂₅ ×Io ₅₄ , and these are expressed by the formula In, V _BEQ20 ≒
V _BEQ49 can be replaced with the remaining _VR24 and _VR25 . That is, V′R ₂₄ = R ₂₄ ×Io ₅₃ ≧V _CE sat _Q20 …… V′R ₂₅ = R ₂₅ ×Io ₅₃ ≧V _CE sat _Q22 …….

As mentioned above, the saturated collector-emitter voltage of transistors Q ₂₀ and Q ₂₂ is about 0.2V, so
V′ _R24 , V′ _R25 exceeds 0.2v, and R ₂₄ , R ₂₅ and
Considering the variations in Io ₅₃ and Io ₅₄ , it would be a good idea to set it to 0.25v, an increase of 10 to 20%. On the other hand, resistance
The values of R ₂₄ and R ₂₅ should be 4kT/q100mv _pp (k: Boltzmann constant, T: absolute temperature, q: 0 Crohn's force) or more in order to perform the switching operation of the double balanced transistor and maintain the differential saturation characteristics. It is necessary to be able to inject an amplitude of approximately R ₂₅ /R ₂₇ ,
It is determined by the resistance ratio of R ₂₄ /R ₂₆ . As an example,
If R ₂₅ = R ₂₅ = 5k, R ₂₇ = R ₂₆ = 22k, low voltage
Even considering Vcc = 1.8V, a switching signal of about 300 mv _pp can be supplied to the base of the double balanced differential upper switching transistor. Therefore R ₂₄ = R ₂₅ =
5k, it is recommended to set Io ₅₃ = Io ₅₄ = 50 _μA to achieve V' _R24 = V' _R25 = 0.25v. When the constant current source according to the present invention is added, the above-mentioned switching signal level decreases slightly due to _V'R24 = _V'R25 , but it is still sufficient at 280mv _pp .

The input versus distortion characteristics of the demodulation circuit shown in Figure 4 are shown in Figure 5.
As shown in the figure. In this way, the transmission distortion of the double-balanced differential amplifier is 1/2 that of the conventional example, and low distortion can be achieved despite the low power supply voltage.

FIG. 6 shows another implementation example. In this implementation example, a circuit 70 for adjusting the degree of separation of right and left channel signal components is built into an integrated circuit, and the other configurations are the same as in FIG. Separation degree adjustment circuit 70
are transistors 59, 60 and resistors 61, 6
A composite signal is supplied to the bases of transistors 59 and 60, and the collector of transistor 50 is connected to terminal 10, and the collector of transistor 60 is connected to terminal 11. Since this circuit 70 is connected in parallel to the transistors 30 and 31, a sufficient degree of isolation can be obtained even with low power supply voltage operation without impairing low voltage operation.

The present invention has been explained using a double balanced differential amplifier used in a stereo demodulation circuit as an example.
This type of transistor circuit is used for purposes other than stereo demodulation, and this description can be applied in the same way.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an FM multiplex demodulator, Fig. 2 is a specific circuit diagram showing a conventional example, Fig. 3 is a characteristic diagram of the conventional example, and Fig. 4 is a circuit showing an embodiment of the present invention. 5 is a characteristic diagram of the circuit shown in FIG. 4, and FIG. 6 is a circuit diagram showing another embodiment of the present invention. 1...Signal source, 2...IC block, 3,1
0, 11... terminal, 4... demodulator, 5... phase comparator, 6... LPF, 7... VCO, 8, 9... frequency divider, 12, 13, 24, 25, 26, 27 ,4
2, 38, 32, 33, 57, 58, 61, 6
2,63...Resistor, 14,15...Capacitor,
20, 21, 22, 23, 28, 29, 30, 3
1, 36, 37, 49, 50, 51, 52, 4
4, 45, 46...transistor, 35...diode, 34...bias source, 39,40,4
7, 52, 53...constant current source.

Claims (1)

[Claims] 1 The first and second components constituting the first differential amplifier
and two transistors constituting a second differential amplifier, the base and collector of one transistor being connected to the base of the first transistor and the collector of the second transistor, respectively, and the base and collector of one transistor being connected to the base of the first transistor and the collector of the second transistor, respectively. a first series connection comprising third and fourth transistors whose bases and collectors are connected to the base of the second transistor and the collector of the first transistor, respectively, a first resistor and a first constant current source; a second series connection circuit including a second resistor and a second constant current source, and a connection point between the first resistor and the first constant current source is connected to the first transistor. connected to the base of
A connection point between the second resistor and the second constant current is connected to the base of the second transistor,
A first signal is supplied to the emitter junctions of the first and second transistors, a bias current is supplied to the emitter junctions of the third and fourth transistors, and the bases of the first and second transistors are supplied with a bias current. A second signal is supplied between the first and
and a transistor circuit, wherein outputs are taken out from the collectors of the second transistor and the second transistor, respectively.