JPH04202074A - Ceramic substrate for thin film - Google Patents

Ceramic substrate for thin film

Info

Publication number
JPH04202074A
JPH04202074A JP33559690A JP33559690A JPH04202074A JP H04202074 A JPH04202074 A JP H04202074A JP 33559690 A JP33559690 A JP 33559690A JP 33559690 A JP33559690 A JP 33559690A JP H04202074 A JPH04202074 A JP H04202074A
Authority
JP
Japan
Prior art keywords
ceramic substrate
thin film
photomask
holes
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33559690A
Other languages
Japanese (ja)
Inventor
Mitsuyoshi Endo
光芳 遠藤
Noriko Nakagawa
中川 法子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP33559690A priority Critical patent/JPH04202074A/en
Publication of JPH04202074A publication Critical patent/JPH04202074A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0073Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To increase the accuracy of positioning of a photomask by forming recessed marks for positioning in the surface of a ceramic substrate on which a circuit layer is formed. CONSTITUTION:The required number of green sheets 1a of AlN, Al2O3, etc., are molded, through holes acting as via holes 3 after firing are pierced in the sheets 1a by punching or other method and holes acting as marks 4 for positioning a photomask are pierced in the sheet 1a for the uppermost layer. The through holes are filled with electrically conductive paste and a circuit layer is formed on the surface of each of the sheets 1a by printing with electrically conductive paste. The sheets 1a are then laminated, press-bonded and fired to obtain a ceramic substrate 1. A thin circuit layer 6 and a photosensitive resist film are successively formed on the substrate 1 and exposure through a photomask and etching are carried out to form a desired circuit.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は、薄膜配線層形成用のセラミックス基板に関す
る。
Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a ceramic substrate for forming a thin film wiring layer.

(従来の技術) 最近のVLSIに見られるように、半導体素子の高集積
化が進むにつれて、半導体素子か搭載されるセラミック
ス基板の表面に形成する導体層は、i’ri密麿化する
必要か牛しており、微細配線を形成することが求められ
ている。このような微細配線の形成を可能にする導体層
としては、真空蒸着法やスパッタリング法等の薄膜法を
適用して形成した薄膜導体層が適している。
(Prior art) As semiconductor devices become more highly integrated, as seen in recent VLSIs, it becomes necessary to make the conductor layer formed on the surface of the ceramic substrate on which the semiconductor device is mounted more dense. Therefore, it is required to form fine wiring. A thin film conductor layer formed by applying a thin film method such as a vacuum evaporation method or a sputtering method is suitable as a conductor layer that enables the formation of such fine wiring.

このような薄膜配線層を有するセラミックス基板は、例
えば以下のようにして作製される。
A ceramic substrate having such a thin film wiring layer is produced, for example, as follows.

すなわちます、内部配線を有するセラミックス基板の表
面に、真空蒸着法やスパッタリング法等によって一様に
薄膜導体層を形成する。次いで、薄膜導体層上に感光性
レジスト膜を形成し、このレジスト膜をフォトマスクを
利用して露光する。
That is, first, a thin film conductor layer is uniformly formed on the surface of a ceramic substrate having internal wiring by vacuum evaporation, sputtering, or the like. Next, a photosensitive resist film is formed on the thin film conductor layer, and this resist film is exposed using a photomask.

この後、上記露光後のレジスト膜をマスキング膜として
エツチングを施し、所望形状の薄膜配線層を形成する。
Thereafter, etching is performed using the exposed resist film as a masking film to form a thin film wiring layer in a desired shape.

(発明か解決しようとする課題) ところで、上記レジスト膜を露光する際に用いるフォト
マスクの位置合せは、通常、セラミックス基板内の配線
網として利用されるピアホールと、フォトマスク上のパ
ターンとを合せることによって行っている。
(Problem to be solved by the invention) By the way, the alignment of the photomask used when exposing the above-mentioned resist film is usually done by aligning the pattern on the photomask with the peer hole used as a wiring network in the ceramic substrate. It is done by doing this.

しかしながら、薄膜形成時点において上記ピアホール内
には導電性物質が充填されているため、セラミックス基
板とピアホール内に充填された導電性物質との色調差が
小さい場合や、セラミックス基板表面に形成した薄膜導
体層の厚さか多少厚くなったような場合には、ピアホー
ル自体を識別することか困難となり、フォトマスクの位
置合せ精度か低下してしまうという問題があった。
However, since the above-mentioned peer holes are filled with a conductive substance at the time of thin film formation, there are cases where the difference in color tone between the ceramic substrate and the conductive substance filled in the peer holes is small, or when the thin film conductor formed on the surface of the ceramic substrate When the thickness of the layer becomes somewhat thicker, it becomes difficult to identify the pier hole itself, resulting in a problem in that the alignment accuracy of the photomask decreases.

特に、薄膜導体層上に金属メツキ層等を形成した場合に
は、フォトマスクの位置合せが困難となってしまう。
In particular, when a metal plating layer or the like is formed on the thin film conductor layer, alignment of the photomask becomes difficult.

本発明は、このような課題に対処するためになされたも
ので、ピアホールの識別が困難な場合においても、フォ
トマスクの位置合せを高精度に行うことを可能とした薄
膜用セラミックス基板を提供することを目的とするもの
である。
The present invention has been made to address such problems, and provides a ceramic substrate for thin films that makes it possible to align a photomask with high precision even when it is difficult to identify peer holes. The purpose is to

[発明の構成コ (課題を解決するだめの手段) 本発明の薄膜用セラミックス基板は、表面に薄膜法によ
る配線層が形成される薄膜用セラミックス基板において
、前記配線層が形成されるセラミックス基板表面に、凹
形状のフォトマスク位置合せ用マークが設けられている
ことを特徴とするものである。
[Structure of the Invention (Means for Solving the Problems)] The ceramic substrate for thin films of the present invention is a ceramic substrate for thin films on which a wiring layer is formed by a thin film method, in which a ceramic substrate surface on which the wiring layer is formed. The device is characterized in that a concave photomask alignment mark is provided on the photomask.

(作 用) 本発明の薄膜用セラミックス基板においては、凹形状の
フォトマスク位置合せ用マークを設けているため、セラ
ミックス基板表面に薄膜配線層を形成した後にも、フォ
トマスク位置合せ用マークを容易に認識することができ
る。したがって、フォトマスクの位置合せを高精度に行
うことが可能となる。
(Function) In the thin film ceramic substrate of the present invention, since the concave photomask alignment mark is provided, the photomask alignment mark can be easily set even after the thin film wiring layer is formed on the surface of the ceramic substrate. can be recognized. Therefore, it becomes possible to align the photomask with high precision.

(実施例) 次に、本発明の実施例について図面を参照して説明する
(Example) Next, an example of the present invention will be described with reference to the drawings.

第1図は、本発明の一実施例の薄膜用セラミックス基板
を示す断面図である。
FIG. 1 is a sectional view showing a thin film ceramic substrate according to an embodiment of the present invention.

同図において、1はアルミナ焼結体、窒化アルミニウム
焼結体、炭化ケイ素焼結体等の各種のセラミック焼結体
からなるセラミックス基数である。
In the figure, 1 is a ceramic base made of various ceramic sintered bodies such as an alumina sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body.

このセラミックス基板1は、複数のセラミックス層1a
を同時焼成によって多層化したものである。
This ceramic substrate 1 includes a plurality of ceramic layers 1a
It is multi-layered by simultaneous firing.

このセラミックス基板1は、内部配線を有するものであ
る。この内部配線は、各セラミックス層]a上に設けら
れた接地層や電源層等を含む内部配線層2と、これら内
部配線層2を電気的に接続するピアホール3とによって
構成されている。
This ceramic substrate 1 has internal wiring. This internal wiring is constituted by an internal wiring layer 2 including a ground layer, a power supply layer, etc. provided on each ceramic layer]a, and a peer hole 3 that electrically connects these internal wiring layers 2.

そして、最上層のセラミックス層1aには、第2図に示
すように、穴状のフォトマスク位置合せ用のマーク4が
対角上にそれぞれ設けられている。
As shown in FIG. 2, in the uppermost ceramic layer 1a, hole-shaped photomask alignment marks 4 are provided diagonally.

上記フォトマスク位置合せ用マークは、上述したような
穴形状のマーク4に限らず、例えば第2図および第3図
に示すような溝状のマーク5を用いることも可能である
等、凹形状を有しかつ平面位置を規定することが可能な
ものであれば、各種形状のマークを用いることができる
The above-mentioned photomask alignment mark is not limited to the hole-shaped mark 4 as described above, but it is also possible to use a groove-shaped mark 5 as shown in FIGS. 2 and 3, for example, or a concave shape. Marks of various shapes can be used as long as they have a shape and can define the planar position.

上記したような薄膜用セラミックス基板1は、例えば以
下のようにして製造される。
The thin film ceramic substrate 1 as described above is manufactured, for example, as follows.

ます、窒化アルミニウムや酸化アルミニウム等からなる
クリーンシート(la)を必要数成形し、= 5− 各グリーンシートに対応するセラミックス層に応じて、
焼成後にピアホール3となるスルーホールをパンチング
等によって形成する。
First, form the required number of clean sheets (LA) made of aluminum nitride, aluminum oxide, etc., and form = 5- according to the ceramic layer corresponding to each green sheet.
A through hole that will become the pier hole 3 after firing is formed by punching or the like.

この際、最上層のセラミックス層1aとなるグリーンシ
ートには、フォトマスク位置合せ用のマーク4となる孔
も同時に形成する。また、溝状のフォトマスク位置合せ
用マーク5の場合にも、グリーンシートの段階で形成す
る。
At this time, holes that will become marks 4 for photomask alignment are also formed at the same time in the green sheet that will become the uppermost ceramic layer 1a. Furthermore, in the case of the groove-shaped photomask alignment mark 5, it is also formed at the green sheet stage.

次に、各スルーホールに導電性ペーストを充填すると共
に、各グリーンシート表面に導電性ペーストを印刷する
ことによって配線層を形成する。
Next, a wiring layer is formed by filling each through hole with a conductive paste and printing the conductive paste on the surface of each green sheet.

上記スルーホールへの充填の際、フォトマスク位置合せ
用マークとなる孔や溝内には導電性ペーストを充填せず
、空洞状態を維持させる。
When filling the through-holes, conductive paste is not filled into the holes and grooves that serve as photomask alignment marks, and the hollow state is maintained.

この後、スルーホール内への充填や印刷配線層の形成が
行われた複数のグリーンシートを、フォトマスク位置合
せ用マークとなる孔や溝が形成されたグリーンシートが
最上層となるように積層し、圧着して一体化した後、使
用したセラミックスに応じた芥囲気および温度で焼成し
て、複数のセラミックス層]aを一体化すると共に、ピ
アホール3および内部配線層2を形成する。
After this, multiple green sheets with through-holes filled and printed wiring layers formed are stacked so that the green sheet with holes and grooves that serve as photomask alignment marks is the top layer. After being crimped and integrated, they are fired at an atmosphere and temperature depending on the ceramic used to integrate the plurality of ceramic layers [a] and form the pier holes 3 and the internal wiring layer 2.

このようにして、薄膜形成表面に凹形状のフォトマスク
位置合せ用マーク4を有し、−かつ内部配線が設けられ
たセラミックス基板]かi!7られる。
In this way, a ceramic substrate having a concave photomask alignment mark 4 on the surface on which a thin film is formed and provided with internal wiring] or i! 7.

上記セラミ・シクス基板1に対しては、第5図に示すよ
うに、フォトマスク位置合せ用マーク4が設けられた側
の表面A上に、薄膜法によって配線層6を形成する。こ
の薄膜配線層6の形成方法としては、真空蒸着法、レー
ザー蒸着法、スパッタ法、CVD法、分子線エピタキシ
ー法等の各種薄膜形成法を適用することができる。
As shown in FIG. 5, a wiring layer 6 is formed on the surface A of the ceramic six substrate 1 on the side where the photomask alignment marks 4 are provided by a thin film method. As a method for forming the thin film wiring layer 6, various thin film forming methods such as a vacuum evaporation method, a laser evaporation method, a sputtering method, a CVD method, and a molecular beam epitaxy method can be applied.

上記実施例のセラミックス基板1では、上述したように
表面に薄膜配線層6を形成した後においても、フォトマ
スク位置合せ用マーク4内に空洞部7が残存するため、
ピアホール4を識別できないような場合においても、フ
ォトマスク位置合せ用マーク4は目視等によって容易に
認識することができる。
In the ceramic substrate 1 of the above embodiment, even after the thin film wiring layer 6 is formed on the surface as described above, the cavity 7 remains within the photomask alignment mark 4.
Even in a case where the peer hole 4 cannot be identified, the photomask alignment mark 4 can be easily recognized by visual inspection or the like.

そして、上記薄膜配線層6上に感光性レジスト膜を形成
し、このレジスト膜をフォトマスクを利用して露光する
。この際、レジスト膜の形成後においても、フォトマス
ク位置合せ用71−り4内には空洞部が残存するため、
このフォトマスク位置合せ用マーク4とフォトマスクの
パターンとを合せることによって、フォトマスクの位置
合せを高精度に行うことが可能となる。この後、上記露
光後のレジスト膜をマスキング膜としてエツチングを施
し、所望形状の回路を形成することにより、高精度かつ
高精細な配線網が得られる。
Then, a photosensitive resist film is formed on the thin film wiring layer 6, and this resist film is exposed using a photomask. At this time, even after the resist film is formed, a cavity remains in the photomask alignment 71-4.
By aligning this photomask alignment mark 4 with the pattern of the photomask, it becomes possible to align the photomask with high precision. Thereafter, etching is performed using the exposed resist film as a masking film to form a circuit of a desired shape, thereby obtaining a highly accurate and fine wiring network.

このように、上記実施例の薄膜用セラミックス基板1に
おいては、予め薄膜配線層6を形成する側の表面に、凹
状のフォトマスク位置合せ用マーク4を設けているため
、ピアホール4を識別できないような場合においても、
フォトマスクを高精度に位置合せすることが可能となる
In this way, in the thin film ceramic substrate 1 of the above embodiment, the concave photomask alignment mark 4 is provided in advance on the surface on the side where the thin film wiring layer 6 is to be formed, so that the peer hole 4 cannot be identified. Even in cases where
It becomes possible to align the photomask with high precision.

[発明の効果] 以上説明したように本発明の薄膜用セラミックス基板に
よれば、従来フォトマスクの位置合せに使用していたピ
アホールの識別が困難な場合においても、フォトマスク
の位置合せを高精度に行うことか可能となる。よって、
薄膜法による高精度かつ高精細な配線網を有したセラミ
ックス基板を容品に得ることか可能となる。
[Effects of the Invention] As explained above, according to the thin film ceramic substrate of the present invention, even when it is difficult to identify the peer holes conventionally used for photomask alignment, it is possible to align photomasks with high precision. It becomes possible to do so. Therefore,
It becomes possible to obtain a ceramic substrate with a high-precision and high-definition wiring network using the thin film method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の薄膜用セラミックス基板の
構成を示す断面図、第2図はその平面図、第3図は本発
明の他の実施例の薄膜用セラミックス基板の構成を示す
断面図、第4図はその平面図、第5図は本発明の一実施
例の薄膜用セラミックス基板に薄膜配線層を形成した状
態を示す断面図である。 1・・・・・・セラミックス基板、1a・・・・・・セ
ラミック ゝス層、2・・・・・・内部配線層、3・・
・・・・ピアホール、4.5・・・・・・フォトマスク
位置合せ用マーク、6・・・・・・薄膜配線層。 出願人      株式会社 東芝 代理人 弁理士  須 山 佐 − −9= 第1図 粥 3 図
FIG. 1 is a cross-sectional view showing the structure of a ceramic substrate for thin films according to one embodiment of the present invention, FIG. 2 is a plan view thereof, and FIG. 3 is a cross-sectional view showing the structure of a ceramic substrate for thin films according to another embodiment of the present invention. 4 is a plan view thereof, and FIG. 5 is a sectional view showing a thin film wiring layer formed on a thin film ceramic substrate according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Ceramic substrate, 1a... Ceramic base layer, 2... Internal wiring layer, 3...
... Pier hole, 4.5 ... Photomask alignment mark, 6 ... Thin film wiring layer. Applicant Toshiba Corporation Representative Patent Attorney Sa Suyama − −9= Figure 1 Congee 3 Figure

Claims (1)

【特許請求の範囲】 表面に薄膜法による配線層が形成される薄膜用セラミッ
クス基板において、 前記配線層が形成されるセラミックス基板表面に、凹形
状のフォトマスク位置合せ用マークが設けられているこ
とを特徴とする薄膜用セラミックス基板。
[Scope of Claims] In a thin film ceramic substrate on which a wiring layer is formed by a thin film method, a recessed photomask alignment mark is provided on the surface of the ceramic substrate on which the wiring layer is formed. Ceramic substrate for thin films featuring:
JP33559690A 1990-11-30 1990-11-30 Ceramic substrate for thin film Pending JPH04202074A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33559690A JPH04202074A (en) 1990-11-30 1990-11-30 Ceramic substrate for thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33559690A JPH04202074A (en) 1990-11-30 1990-11-30 Ceramic substrate for thin film

Publications (1)

Publication Number Publication Date
JPH04202074A true JPH04202074A (en) 1992-07-22

Family

ID=18290357

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33559690A Pending JPH04202074A (en) 1990-11-30 1990-11-30 Ceramic substrate for thin film

Country Status (1)

Country Link
JP (1) JPH04202074A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521069B1 (en) * 1999-01-27 2003-02-18 Matsushita Electric Industrial Co., Ltd. Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board, and manufacturing method of double-sided wiring board
EP1435658A4 (en) * 2001-10-10 2006-10-25 Tokuyama Corp SUBSTRATE AND METHOD FOR PRODUCING THE SAME

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521069B1 (en) * 1999-01-27 2003-02-18 Matsushita Electric Industrial Co., Ltd. Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board, and manufacturing method of double-sided wiring board
US6696139B2 (en) 1999-01-27 2004-02-24 Matsushita Electric Industrial Co., Ltd. Green sheet and manufacturing method thereof, manufacturing method of multi-layer wiring board and manufacturing method of double-sided wiring board
EP1435658A4 (en) * 2001-10-10 2006-10-25 Tokuyama Corp SUBSTRATE AND METHOD FOR PRODUCING THE SAME

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