JPH0420214B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of operating an input/output device connected to a computer, and more particularly to a method of calling an operating program for operating the input/output device.

an input/output device, typically connected to a central processing unit;
For example, the operation program (hereinafter referred to as OS) that sends data to and imports data to a CRT display, keyboard, printer, etc.
It is carried out depending on the This OS is as shown in Figure 1.
It can be called in response to a request from input/output device A or B, and a request from each independent user program A, B, or C, and data transmission and reception of input/output device A or B is performed depending on the execution of the OS. It manages user programs A, B, or C, such as executing another user program B while user program A is on standby. However, if the OS is made into a subroutine and placed at the same level as the user program, it will jump to the OS address specified by the user program and send data to be displayed on a CRT display, for example, while the OS is running. When you are
When an interrupt request is received from another input/output device, such as a keyboard, the OS is called by a program that handles the interrupt, causing the OS to stop mid-operation. Therefore, it is necessary to unify OS requests from programs, ie, software, and OS requests from input/output devices, ie, hardware, and treat them at the same level. Conventionally, in order to solve the above-mentioned inconvenience, when accepting an interrupt request from an input/output device or a request from a program,
The CPU automatically sets the interrupt disable flag and
There are some methods that prohibit all interrupts except emergency interrupts such as memory failures based on the flag, but in order to use this method, the interrupt disable flag must be automatically set when an interrupt is accepted. There was a need for a CPU or interrupt control means that could limit the scope of interrupt prohibition, using a CPU with the necessary functions, and not disabling only emergency interrupts that should be enabled even when the OS is running.
Therefore, in a system that does not use such a CPU and interrupt control means, it is impossible to call the OS using this method.

Of course, it is not impossible to accept interrupts from input/output devices while the OS is running, but in this case, the OS must have a complex re-entrance structure in order to maintain the memory contents of various registers, etc. The problem is that it has to be done.

The present invention has been made in view of the above-mentioned points, and the operating program, that is, the OS, is configured to perform processing based on the interrupt with the highest priority among interrupts other than emergency interrupts such as memory failures, and the interrupt is handled by software. from the hardware as well as from the hardware.
OS requests provide a method for calling operating programs that are executed via two-stage interrupts. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention, in which 1 is a central processing unit (CPU), 2 is a main memory,
3 and 4 are input/output devices, 5 and 6 are interfaces, 7 is an address detection means, and 8 is an interrupt control means.

CPU1 is ALU, instruction register,
It consists of a program counter, a memory address register, etc., and sends address data specifying the address of the main memory 2 to the address bus 9.
and is connected via a memory data bus 10. The main memory 2 is RAM, a magnetic disk,
A program stored on a magnetic tape or the like is transferred and stored in advance. The address of the main memory 2 is accessed by address data sent to the address bus 9, and the instruction code stored at that address is sent to the memory data bus 10, or the data sent to the memory data bus 10 is accessed. Remember. Input/output devices 3 and 4 are connected to the data bus 11 connected to the CPU 1 via interfaces 5 and 6, respectively, and the input/output device 3 is, for example, a CRT display.
The input/output device 4 is, for example, a keyboard. The interfaces 5 and 6 have built-in control circuits and memories for controlling the input/output devices 3 and 4 connected thereto.

The address detection means 7 detects that the address data sent to the address bus 9 is address data for accessing a specific address of the main memory 2, for example, 00-77 (OCT), and outputs a high-priority interrupt signal. At the same time as outputting INT0, data for accessing a specific address in the main memory 2, for example address 05 (OCT), is applied to the CPU 1. In addition to the interrupt signal INTT0, interrupt signals INT1 and INT2 are applied to the interrupt control means 8 from the respective interfaces 5 and 6. Interrupt control means 8
determines the priority of interrupt signals INT0, INT0, INT2, and requests an interrupt to CPU1. In addition, when a certain interrupt occurs, the interrupt control means 8 does not accept the interrupt if there is an interrupt request with a lower priority than that interrupt, and the interface 5, 6, etc. requesting the interrupt does not accept the interrupt. into standby mode. When the CPU 1 receives an interrupt, it holds the data of the program counter, connects the output of the address detection means 7 and the data bus 11 to the memory address register, and sends the output to the address bus 9. That is, when an interrupt is accepted, address data output from only those for which the interrupt has been accepted is applied to the main memory 2. Each of the interfaces 5 and 6 outputs predetermined address data to the data bus 11 when an interrupt is accepted, and the address data is sent to the address detection means 7. Specific address detected, 00
-77 (OCT) is accessed, and an OS request is made using that address as the entry point.

Figure 3 is a table showing an example of the allocation of the main memory 2 shown in Figure 2, and the addresses are in octal numbers (OCT).
It is indicated by. 00 detected by address detection means 7
(OCT) to 77 (OCT), the operating program
For input/output devices, user programs, etc. that require an OS, the necessary program entrances are assigned in order of priority, and the OS entrance is assigned address 05. Also, from addresses 00 to 04, there are things with higher priority than the OS, such as emergency programs, and at address 20, there is interface 5, at address 30, interface 6, and at address 77, there is a user program. is assigned to. On the other hand, 100
After the address, an operating program OS, programs for the interfaces 5 and 6, user programs, etc. are assigned.

Next, the operation will be explained with reference to FIGS. 2 and 3.

First, when requesting the operating program OS by a user program, for example, the CPU 1 is caused to perform a predetermined process, the result is output to the input/output device 3,
When displaying on a CRT display, the jump subroutine instruction "JSB77 (I)" in the user program is executed. Then, CPU 1 retains the count contents of the program counter, sets data pointing to "77" specified by the instruction code of the jump subroutine instruction in the memory address register, and transfers the data to the address bus 9.
Send to. The address of subroutine "N" is stored at address 77 in the main memory 2, and the address data is transmitted via the memory data bus 10.
is set in the memory address register of CPU1,
Since the data is sent to the address bus 9, address N of the main memory 2 is accessed. This address N is blank and no instruction code is stored.
By executing "JSB77(I)", the data previously held in the program counter, that is, the data to which address "1" of the user program before jumping is added, is stored at address N. Further, at address N+1, an instruction to stop the progress of the program and maintain its operation is stored, and the program is stopped at address N+1.

On the other hand, when data indicating address 77 is sent to the address bus 9 by execution of "JSB77(I)", the address detection means 7 outputs an interrupt request INT0 to the interrupt control means 8. Interrupt control means 8 is INT
If there is no interrupt request with priority higher than 0,
Request an interrupt to CPU1. This request is CPU1
executes the instruction at address N+1 and is accepted when the program is stopped and enters interrupt processing.
At this time, CPU1 writes N+1 to the program counter.
It holds address data and sends data output from the address detection means 7 for accessing address 05 of the main memory 2 to the address bus 9 via the memory address register. A jump instruction “JSBK” is stored at address 05 of main memory 2.
By executing "JSBK", the program jumps to address K in main memory 2. Address K is blank as described above, and address N+1 held in the program counter by executing "JSBK", that is, address data to be executed next after OS processing, is stored at address K. The required operating program OS is stored from address K+1 onwards.
Depending on the execution of this OS, the operations requested by the user program, such as the CPU
The data processed in step 1 is sent to input/output device 3.
Operations such as displaying on a CRT display can be performed.

At the end of the OS program, a return command "RET" is executed, which causes the program to return to the address stored at address N, ie, to the user program.

Next, in the case of an interrupt request from hardware, for example, interrupt request INT1 from interface 5.
If there is no request with a higher priority than the interrupt request INT1, the interrupt control means 8 accepts the interrupt request INT1 and requests the CPU 1 to make an interrupt. When CPU1 accepts an interrupt, execution of the program is stopped, the address of the program at that time is held in the program counter, and
Data bus 11 is connected to memory address registers. On the other hand, when the interrupt request INT1 is accepted, the interface 5 sends predetermined address data, that is, data for accessing address 20, so this address data is sent to the address bus 9 via the memory address register.
Address 20 of main memory 2 is accessed. The jump instruction “JSBL” is stored at address 20,
By executing "JSBL", the L address of main memory 2 is accessed and the L address is blank.
At the address, 1 is added to the pre-interrupt address data held in the program counter and stored. Further, an instruction to stop the progress of the program is stored at address L+1, and the progress of the program is stopped by the execution of address L+1. The above is the interrupt processing based on the interrupt request INT1.

On the other hand, the address detection means 7 detects that address data accessing address 20 is sent to the address bus 9, and outputs an interrupt request ITN0 having a higher priority than the interrupt request INT1. In response to this interrupt request ITN0, an additional interrupt is applied to the CPU 1, and the CPU 1 holds data for accessing the address currently being processed for the interrupt, that is, address L+1, in the program counter, and the address detection means 7
The data accessing address 05 output from the memory address register is sent to the address bus 9 via the memory address register. By executing the jump instruction "JSBK" at address 05, data obtained by adding "1" to the contents of the program counter, that is, address data indicating address "L+1", is stored at address K, and then the operating program OS is executed. .

Similarly to the above case, when the return instruction "RET" is executed at the end of the OS, the program returns to the address stored at address L, that is, the address next to the address before interrupt request INT1 was applied, and the subsequent program is executed. executed.

Interrupt request INT2 from interface 6
Exactly the same operation is performed when there is a problem.

In the above operation, the address detection means 7 detects 05
Data for accessing the address is sent, but this is because the output of the address detection means 7 is a 6-bit output to simplify the hardware.
Since only address 77 can be accessed, address 05 is assigned as the entrance to the operating program OS.
However, by increasing the output bits of the address detection means 7, it is also possible to directly access the address of the OS.

As mentioned above, the software detects that any of addresses 00 to 77 (OCT) has been accessed, requests a high-priority interrupt, and executes the operating program OS in the interrupt processing. The OS can be called from both software and hardware, and it does not accept interrupts from input/output devices while the OS is running. Therefore, OS requests from software and requests from hardware
This makes it possible to handle OS requests in a unified manner. Therefore, it is no longer necessary to configure the OS part to be executed in response to a request from a program and each OS part to be executed in response to an interrupt request from each input/output device as separate programs. By standardizing the same processing routines in multiple OS parts and grouping each OS part together, the OS execution will not stop mid-way and will operate reliably, making it possible to downsize the OS. It becomes possible. Furthermore, since no interrupts are accepted from input/output devices while the OS is running, there is no need for the OS to have a complicated re-entrance structure, and the OS program itself can be simplified.
In particular, even in systems where the CPU does not have a function to automatically set the interrupt disable flag when accepting an interrupt, or where the CPU or interrupt control means cannot limit the interrupt disable range, the OS can be executed reliably as before. becomes possible.

[Brief explanation of drawings]

FIG. 1 is a system diagram for explaining the operating program OS, FIG. 2 is a program diagram showing an embodiment of the present invention, and FIG. 3 is a main memory allocation table. 1...Central processing unit, 2...Main memory, 3, 4...
Input/output device, 5, 6...interface, 7...
... Address detection means, 8 ... Interrupt control means, 9
...Address bus, 11...Memory data bus, 11...Data bus.

Claims (1)

[Claims] 1. A method for calling an input/output operation program that calls an operation program stored in main memory in response to a request from the input/output device or a user program in order to operate multiple input/output devices connected to a central processing unit. In this step, an interrupt destination address from the input/output device and a jump destination address from the user program are assigned to a predetermined address range of the main memory, and it is determined that an address within the predetermined address range of the main memory is accessed. address detection means for detecting and generating an interrupt request with a higher priority than an interrupt request from an input/output device; and an address detection means for inputting a plurality of interrupt requests from the address detection means and the input/output device, and an interrupt control means for sending an interrupt signal to the processing unit, and when requesting a call from the input/output device, generates a first interrupt request and moves the access of the central processing unit to the interrupt destination address. generate a second interrupt request from the address detection means by accessing the interrupt destination address, and
When the user program requests a call, the access of the central processing unit is shifted to the jump address, and the access to the jump address causes the address detecting means to generate an interrupt request; A method for calling an input/output operation program, characterized in that the operation program is also called in response to an interrupt request from the address detection means.