JPH04205247A - Lock transfer system - Google Patents

Abstract

PURPOSE:To execute lock transfer without previously setting a throw-off mode to a non throw-off mode by providing a lock transfer control function having a specified function. CONSTITUTION:A lock transfer control function 4 is provided at a bus interface circuit BIF connecting a processor muP through a local bus 12. When a throw-off mode operating function 2 is effective and access received from the local bus 12 is caused by lock transfer, the lock transfer control function 4 transfers the access to a system bus 11 without releasing the local bus 12 when this access is received, and after the access of the system bus 11 is completed, the local bus 12 is released. Thus, the lock transfer can be executed without setting the throw-off mode to the non throw-off mode in advance.

Description

[Detailed Description of the Invention] [Summary] Regarding a lock transfer method for performing lock transfer in a bus interface circuit, when lock transfer is performed with the bus interface circuit set to a non-permanent mode, there is no non-permanent transfer. A multiprocessor system in which each processor is connected to a system bus through a bus interface circuit connected via a local bus. When each bus interface circuit in , has a function of non-permanent mode operation and a non-permanent mode operation function, as well as a function of detecting the lock transfer state of the local bus and performing lock transfer to the system bus, When the access received from the local bus is locked when the mode function is enabled, the access is transferred to the system bus without immediately releasing the local bus, and the local bus is released after the system bus access is completed. It is configured by providing functions.

[Industrial application field]

The present invention relates to a lock transfer method for performing lock transfer of data, etc. in a circuit that interfaces between a system bus and a local bus under the system bus.

In a multiprocessor system with common memory, exclusive control must be performed to protect common resources, and one method for achieving such exclusive control is test and set control (T&Sil1m). .

The T&5Il111f stores the usage status of common resources using a part of the common memory as a key, and when using a common resource, it first reads the key, and if it is in use, it does not use the common resource and marks it as an unused resource. In this case, the common resource is exclusively controlled by writing the key as being in use and then using it.

However, in T&5illi[, there is a possibility that another processor etc. may read or write the key between reading and writing of the key, so T&S
During control, a lock transfer state may be used to restrict access to the key by other processors. Access in this una-lock transfer state is called lock transfer.

Also, when transferring large amounts of data at high speed, it is necessary to perform multiple accesses in succession, but in the case of a system that performs bus arbitration for each access,
Since other processors may interrupt and use the bus between accesses, the transfer speed cannot be guaranteed. Therefore, during these accesses, a method of solving the problem is to set a lock transfer state and restrict access by other processors.

Also, when a processor writes to the common memory via the system bus, the processor writes from the local bus via the bus interface circuit, but in this case, the local bus control method is to keep the local memory until the write is completed. There is a non-disable mode in which the bus is not released, and a non-disable mode in which the local bus is released after write access to the system bus via the bus interface circuit.

In the lock transfer method, when lock transfer is performed while the bus interface circuit is set to non-disconnect mode, it is possible to perform lock transfer without setting the non-disconnect mode to non-disconnect mode in advance. requested.

[Conventional technology]

FIG. 6 illustrates the configuration of a multiprocessor system.

In FIG. 6, a plurality of central processing units CPU.

CPU U, -, CP Ull and central processing unit C
P.U.

A common memory CM, CM, , CM, which can be commonly accessed by the CPUs, , . ,−,CM, is shown connected via a system bus 11 to a bus arbiter BA that arbitrates access to. The configuration shown in FIG. 6 is a general one, and other input/output (10) devices and the like may be provided.

FIG. 7 shows the configuration of each central processing unit.
, l and is shown connected to the system bus 11 from the bus interface circuit BIF, l.

FIG. 8 shows an example of the connection between the bus interface circuits and the bus arbiter, in which the bus interface circuits BIF, . . . belong to each central processing unit and the common memory.
BI Fz, -, B IF, , and the bus arbiter BA respectively send request signals RE Q r, RE Qz, '-RE Q, which are bus right request signals for individual lines.
stomach. , and an acknowledge signal A which is a bus master notification signal.
It is shown that they are connected via CK,,ACKz,-ACK,□. The bus arbiter BA performs the function of arbitrating between multiple bus master requests.

The operation of the system bus in this case, that is, the transfer procedure of the system bus, is performed in the following order.

(2) The central processing unit CPU asserts the request signal REQ and requests the bus right.

(2) The bus arbiter BA asserts an acknowledge signal ACK in response to the request signal REQ.

(2) When the central processing unit CPU receives the acknowledge signal ACK, it becomes the bus master, negates the request signal REQ, and starts data transfer. During the data transfer period, the bus mask sends a transfer start signal S to the system bus.
Notification is made by asserting BS and transfer end signal CPT for one cycle each.

(2) When the bus arbiter BA receives the transfer end signal CPT, it negates the acknowledge signal ACK and notifies the end of the bus right.

The local bus operates as follows.

■ The microprocessor μP sets the transfer start signal BS to 1.
It asserts the cycle and outputs the address, etc.

(2) When receiving the transfer start signal BS, the bus interface circuit BIF performs different operations depending on whether it is in the non-interactive mode or the non-interactive mode.

FIG. 9 explains the operation of the bus interface circuit in the non-permanent mode, and shows a time chart during write access.

In other words, in this case, ■ When the local bus transfer start signal BS is received,
The bus interface circuit BIF performs the transfer to the system bus according to the procedure described above, and waits for an answer.

(2) When an answer is received from a slave device on the system bus, the answer wait state is released, a reception completion signal DC (Data Complete) on the local bus is asserted, and the transfer process is completed.

FIG. 10 explains the operation of the bus interface circuit in the constant mode. In other words, in this case, ■ Upon receiving the local bus transfer start signal BS, the bus interface circuit BIF immediately sends the reception completion signal D.
C is asserted and transferred to the system bus according to the procedure described above. In this case, there is no waiting for an answer.

FIG. 11 shows the format of system bus commands and answers.

The command or answer is the first data to be transferred while the transfer start signal SBS is asserted, and includes a transfer source ID and a transfer destination ID.

Indicates whether the answer is essential or unnecessary, and whether it is a command or an answer.

FIG. 12 shows the configuration of the bus interface circuit, in which the buffers 21 . Transmission FIFO memory 22
．． Buffers 23, 24 . Reception FIFO memory 25. Buffer 26. Reception control section 27, FIFO @ control section 28. Transmission control unit 29. Reception control unit 30. F I F011
J? Part 11 31. It is shown that it has a transmission control section 32.

Transmission data is transferred from the local bus to the system bus via a buffer 21, a transmission FIFO memory 22, and a buffer 23. On the other hand, the received data is transferred from the system bus to the buffer 24. Reception FIFO memory 25. The signal is sent to the local buffer via the buffer 26.

At this time, the reception control unit 27 determines the reception of transmission data from the local bus to the system bus, and the FIFO control unit 2
8 is the address of the buffer 21 based on this determination result,
It controls writing data into the transmission FIFO memory 22. When the transmission control unit 29 detects writing to the transmission FIFO memory 22 under the control of the FIFO control unit 28,
Control is performed so that the address and data written in the transmission FIFO memory 22 are read out and sent to the system bus via the buffer 23.

Further, the reception control unit 30 determines whether or not to receive reception data from the system bus, and the FIFO control unit 31 transfers the data in the buffer 24 to the reception F.
Controls writing to the IFO memory 25. Transmission control section 3
2 performs control so that the data written in the reception FIFO memory 25 is read out and sent to the local bus via the buffer 26.

FIG. 13 shows the configuration of the local bus reception control section 27, in which the reception determination section 35. Input address control section 36. It is shown that the input display control section 37 has a DCIJm section 38.

The reception control unit 27 receives the transfer start signal BS from the local bus, and when the output of the reception determination unit 35 indicates reception, the reception control unit 27 receives the transfer start signal BS from the input address control unit 36 to the FIFO control unit 28.
, a signal for updating the address of the transmission FIFO memory 22 is asserted, and the input completion display section 37 indicates that the F
A signal indicating that the input has been completed is asserted to the IFO control unit 28.

The DC control unit 38 immediately asserts the reception completion signal DC to the local bus when in the no call mode, and outputs the answer request signal to the FIFO II 1111 unit 28. Further, in the non-talking mode, the reception completion signal DC is not asserted, and the answer request signal is output to the FIFO control unit 28.

FIG. 14 shows the configuration of a conventional DC control section 38.

The no-mark register 41 is set in the no-mark state. The AND circuit 42 calculates the logical product of the output of the unmarked register 41 and the write access condition (read/write signal RW="0"), and the AND circuit 43 calculates the logical product of the output of the AND circuit 42 and the reception determination section 35.
The result of calculating the logical product with the reception judgment result is °“1
When ``'', it is determined that the light is in a continuous light state.

At this time, the AND circuit 45 calculates the logical product of the signal synchronized with the transfer start signal BS of the local bus via the flip-flop (FF) 44 and the determination result of the write without interruption. F
F) Assert the reception completion signal DC via 46. Therefore, in the release state (, the release register 41 is “
0'', the reception completion signal DC is not asserted depending on the transfer start signal BS of the local bus.

When releasing the local bus after receiving the answer, a reception completion signal DC is asserted via the OR circuit 47 in response to a signal from the transmission control section 29.

FIG. 15 shows the structure of the FIFO control section 28, and shows the structure of the FIFO control section 28 for the transmission FIFO memory 22, and shows the structure of the FIFO control section 28 for the input address section 51. Output address section 52. Queue buffer (1)53. Queue buffer (2) 54, Queue buffer (3) 55
, input completed display section 56. Output method display section 57° mismatch detection section 58. It is shown that it has a match detection section 59.

The input address section 51 consists of a counter, and the reception control section 2
Each time an update signal is input from 7, it is incremented by "+1" to indicate the write address of the transmission FIFO memory 22. The output address section 52 is composed of a counter, and each time an update signal is input from the reception control section 29, "+
1'' indicates the read address of the transmission FIFO memory 22.

The queue buffer (1) 53 is a FIFO memory TJ for transmission.
The address obtained by adding 1 to the last input address written in 22 is recorded. The queue buffer (2) 54 records information on whether or not an answer is required from the reception control unit 27. The queue buffer (3) 55 records the lock state of the local bus.

The input completion display section 56 consists of a counter, and is incremented by "+1" each time data is received from the local bus, indicating that the data has been written to the transmission FIFO memory 22. The output method display section 57 consists of a counter, and is incremented by 1j every time data is transferred to the system bus, indicating that reading from the transmission FIFO memory 22 has been completed.

Queue buffer (1) 53 to queue buffer (3) 55
Writing and reading are performed in accordance with the counter values of the manual display section 56 and the output display section 57.

The transmission FIFO memory 22 operates as follows.

■ When a manual address update signal is received from the reception control unit 27, the transmission FIFO memory 22 asserts the write enable signal WE, and the input address unit 51
Update the value of

■ Queue buffer (1) 53 ~ Queue buffer (3)
Predetermined information is recorded in 55.

(2) Set the counter on the input completion display section 56 to r+IJL, indicating that the input has been completed.

■ The mismatch detection section 58 compares the counter value of the input display section 56 and the counter value of the output method display section 57, and if the value of the input display section 56 is larger (when they do not match), Since this indicates that there is something to be transferred, this information is sent to the transmission control section 29.

■ Transmission FIF indicated by the counter value of the output method display section 57
The information on the number of reads from the O memory 22 is sent to the transmission control unit 2.
At the same time, the match detection unit 59 sends the address to the output address unit 5.
The counter value of No. 2 is compared with the value of the queue buffer (1) 53, and information on the comparison result is sent to the transmission control section 29.

(2) The transmission control unit 29 reads the transmission FIFO memory 22 until the output address and the value of the queue buffer (1) 53 match, and transfers it to the system bus.

(2) When the transmission is completed, the transmission control unit 29 increments the counter value of the output method display unit 57 by “+l”. As a result, the value in the input display section 56 and the value in the output method display section 57 match,
Transferred.

FIG. 16 shows the configuration of the transmission control mm 29, and shows the transmission control section 29 for the transmission FIFO control section 28.
The configuration of the REQ control unit 61°SBS! [Part 1 62
．． CPT@Obe63. Transferring representation part 64. It is shown that it has a lock line control section 65.

The operation of the transmission control section 29 is performed as follows.

■ In the FIFOl#Im section 28, the mismatch detection section 5
8, the inputted display section 56. When information indicating that the values in the output display section 57 do not match is sent to the REQ control section 61, the REQ control section 61 asserts a request signal REQ to the system bus.

(2) Upon receiving the acknowledge signal ACK from the bus arbiter BA via the system bus, it negates the request signal REQ and starts transfer.

(2) While receiving the acknowledge signal ACK, it indicates that the bus interface circuit BIF is the bus master, so the buffer 23 is opened. Further, in the SBS control unit 62,
The transfer start signal SBS is asserted from the rise of the acknowledge signal ACK.

(2) When the transfer starts, an output address update signal is sent to the FIFO control unit 28, and the transmission FIFO memory 22 is sequentially read out and transferred to the system bus.

■ When the match detection unit 59 detects a match between the value of the queue buffer (1) 53 of the FIFO control unit 28 and the output address, there is no data to read, so the CPT
The control unit 63 asserts a transfer end signal CPT indicating completion of output to the system bus, thereby terminating the system bus. In addition, the transfer end signal CPT is sent to the FIF○ control unit 28.
By sending the signal to the bus interface circuit BIF and incrementing the counter of the output display section 57 by 1, the internal control of the bus interface circuit BIF is also output.

(2) At this time, since the lock information is recorded in the queue buffer (3) 55, the lock line control unit 65 asserts the system bus lock signal 5LOC when receiving the acknowledge signal ACK.

FIG. 17 shows the configuration of a conventional lock line control section 65.

When the bus interface circuit BIF receives an acknowledge signal ACK from the system bus and becomes the bus master of the system bus, and the value of the queue buffer (3) 55 indicates lock transfer, the AND circuit 71 outputs an acknowledge signal. The logical product of the signal ACK and the output value of the queue buffer (3) 55 is calculated, the OR circuit 72 calculates the logical sum of this and the system bus lock signal LOC, and the AND circuit 73 calculates the logical product of this output and the local bus lock signal LOG. After synchronizing the ANDed value using a flip-flop (FF), the output is outputted as a system bus lock signal 5LOC.

Therefore, when the local bus lock signal LOC is negated, the system bus lock signal 5LOC is also negated.

In this way, in a multiprocessor system in which each processor is connected to the system bus from the local bus via the bus interface circuit, the bus interface circuit receives accesses from the local bus, transfers them to the system bus, and processes system bus accesses. Once completed, the local bus is released.

Conventionally, the operation of the bus interface circuit in this case is that when a lock transfer access is received from the local bus, the system bus is locked when transferring to the system bus, and when the local bus is released from the lock state, the bus interface circuit locks the system bus. First, lock transfer was performed by releasing the lock transfer state of the system bus.

[Problem to be solved by the invention]

However, in the case of a bus interface circuit that has a never-before-seen mode that releases the local bus immediately after receiving an access from the local bus, the local bus is released and the locked transfer state of the local bus is changed before the access is transferred to the system bus. There is a problem in that lock transfer cannot be performed because there is a possibility that the lock transfer state of the system bus is released.

Therefore, if you want to perform a lock transfer when the bus interface circuit is set to the non-display mode, first set the bus interface circuit to the non-display mode, then perform the lock transfer, and then the lock transfer will be performed. Once completed, it was necessary to set the bus interface circuit to silent mode again.

The present invention aims to solve the problems of the prior art, and is to provide a bus interface circuit for a multiprocessor system in which each processor is connected to a system bus via a bus interface circuit, in which the bus interface circuit is connected to the system bus. To provide a lock transfer method capable of executing lock transfer without previously setting a talk mode to a non-talk mode when lock transfer is performed in a state where the talk mode is set.

[Means to solve the problem]

FIGS. 1(a) and 1(b) show the basic structure of the present invention.

As shown in FIG. 1(a), the basic structure of the present invention is as follows:
Processor μP connects to system bus 11 via bus interface circuit BIF connected via local bus 12.
Each bus interface circuit BIF in the multiprocessor system connected to When an access is received from the local bus 12, the disconnection mode operation function 2 immediately releases the local bus 12 and transfers this access to the system bus 11. When detecting when the bus 12 is in the lock transfer state and performing lock transfer to the system bus 11, a lock transfer control function 4 is provided, and when the lock transfer function 2 is enabled, the lock transfer control function 4 is provided. When the received access is due to lock transfer, the access is transferred to the system chair 11 without releasing the local bus 12 upon receiving this access, and the local bus 12 is released after the access to the system bus 11 is completed. This is what I did.

Further, as shown in FIG. 1(C), the present invention is applicable to each processor in a multiprocessor system in which a processor μP is connected to a system bus 11 via a bus interface circuit BIF connected via a local bus 12. The bus interface circuit BIF transfers the access received from the local bus 12 to the system bus 11 by the non-disconnect mode operation function 1, releases the local bus 12 when the access to the system bus 11 is completed, and performs the non-disconnect mode operation function. Local bus 12 by 2
When an access is received from the local bus 12, the local bus 12 is immediately released and the access is transferred to the system bus 11, and the system bus rotor transfer function 3
When detecting when the local bus 12 is in a lock transfer state and performing lock transfer to the system bus 11,
A lock transfer completion detection function 5 is provided, and the local bus 12
A lock transfer termination function 6 is provided, and when the access to the system bus 11 is completed after detecting the completion of the lock transfer, the system bus 1
This is to terminate the locked state of 1.

[Effect]

Each bus interface circuit of a multiprocessor system in which the processors are connected to the system bus via a bus interface circuit connected via a local bus forwards accesses received from the local bus to the system bus in a silent mode. When the access to the system bus is completed, the local bus is released, and when an access is received from the local bus in continuous mode, the local bus is immediately released, and this access is transferred to the system bus, and the local bus is locked. When the access received from the local bus is due to a lock transfer in the uninterrupted mode, when this access is received by lock transfer to the system bus. The access is transferred to the system bus without releasing the local bus, and the local bus is released after the system bus access is completed. When lock transfer is to be performed, lock transfer can be performed without setting the call-only mode to the non-talk mode in advance.

In addition, in a bus interface circuit similar to the one described above, the lock state of the system bus is terminated when the system bus access is completed after detecting the completion of the local bus lock transfer and after detecting the completion of the lock transfer. Therefore, when lock transfer is to be performed with the bus interface circuit set to the constant mode, the lock transfer can be performed without previously setting the constant mode to the non-continuous mode.

〔Example〕

FIG. 2 shows an embodiment of the present invention, and shows the configuration of the DCil1m section 38 in the present invention. The same parts as in FIG. 14 are indicated by the same numbers, and 48 is an AND circuit.

In the embodiment of FIG. 2, the limit register 41 is:
Set when there is no connection. The AND circuit 42 locks the local bus based on the logical product of the output of the discontinuation register 41 and the access condition (read/write signal RW-"θ"). The AND circuit 48 calculates the AND with the inverted value of the signal LOG.
When the result of calculating the logical product of the output of and the reception determination result of the reception determination section 35 is "l", a write without interruption is determined.

At this time, the transfer start signal BS of the local bus is synchronized by the flip-flop (FF) 44, and the AND circuit 45 calculates the AND of this and the determination result of the independent write, and the flip-flop (FF) 46, the reception completion signal DC of the local bus is asserted.

When releasing the local bus after receiving the answer, a reception completion signal DC is asserted via the OR circuit 47 in response to a signal from the transmission control section 29.

As described above, according to the embodiment shown in FIG. 2, when the bus interface circuit BIF is in the constant mode and receives the lock signal LOG, the local bus is immediately activated even if the local bus transfer start signal BS is received. is not released and operates in a non-trivial mode.

FIG. 3 explains the operation of T&S control according to the embodiment of FIG. 2.

In the example of FIG. 3, since T&S control is performed, a read operation is performed first, and then a write operation is performed.

(2) The microprocessor μP asserts the local bus transfer start signal BS for one cycle and outputs an address and the like. At the same time, local bus lock signal LO
G is asserted.

■ Bus interface circuit BIF sends transfer start signal BS
When it receives the request signal REQI, it outputs a request signal REQI to the system bus.

(2) When the acknowledge signal ACK1 is returned from the bus arbiter BA, the bus interface circuit BIF asserts the transfer start signal SBS to the system bus, and transfers the command C specifying the transfer source and destination and the address A to the system bus.

(2) At this time, the bus interface circuit BIF asserts the lock signal 5LOC on the system bus to lock the system bus. When the transfer of the command and address is completed, the transfer end signal CPT is asserted, and the transfer is ended immediately.

■ After that, answer AN and data D from common memory CM.
is returned, but in this case as well, after the request signal REQ2 is output from the common memory CM using the same procedure,
After the acknowledgment signal ACK2 is returned from the bus arbiter BA, the common memory CM asserts the transfer start signal SBS on the system bus and simultaneously outputs the answer AN. At this time, the common memory CM switches the transfer source and transfer destination specified by the command in the answer AN and transfers the data to the system bus. Next, data D from common memory CM
When the transfer is completed, the transfer end signal CPT is asserted.

(2) When the bus interface circuit BIF receives the transfer completion signal CPT, it returns the reception completion signal DC on the local bus, asserts the data line, and transfers the data to the microprocessor μP.

Next, without negating the system bus lock signal 5LOC, the transfer start signal BS is asserted to perform a write operation.

(2) The microprocessor μP asserts the transfer start signal BS and outputs the address and data.

Bus interface circuit BIF receives request signal REQ
When it asserts I and receives the acknowledge signal ACK1 from the bus arbiter BA, it asserts the transfer start signal SBS on the system bus, transfers the command C, address A, and data D to the system bus, and when the transfer ends, Assert transfer end signal CPT.

■ When the request signal REQ2 is asserted from the common memory CM upon completion of the transfer, and the acknowledge signal ACK2 is returned from the bus arbiter BA, the common memory CM
When M asserts a transfer start signal SBS on the system bus and simultaneously outputs an answer AN to complete the transfer, it asserts a transfer end signal CPT.

(2) When the bus interface circuit BIF receives the answer AN, it returns the reception completion signal DC to the local bus and negates the lock signal LOG. By negating the lock signal on the local bus, the lock signal 5LOC on the system bus is negated.

FIG. 4 shows another embodiment of the present invention, and shows the configuration of the lock line control section 65 in the present invention.

The same parts as in FIG. 17 are indicated by the same numbers, and 75.
76 is a flip-flop (FF), 77 to 79 are AND circuits, and 80 is an OR circuit.

In the circuit shown in FIG. 4, the FF 75 samples the lock signal LOG of the local bus, and the AND circuit 77 calculates the AND of this sampled value and the inverted value of the lock signal LOG, thereby negating the lock signal LOG. To detect. Furthermore, OR circuit 80. AND circuit 7B, FF7
When the lock signal LOG is detected to be negated, it is held in FF76 and the transfer end signal CPT is
When , the hold is released. The AND circuit 79 generates an output of the logical product of the signal held in the FF 76 and the transfer end signal CPT.

On the other hand, an AND circuit 71 calculates the logical product of the acknowledge signal ACK and the value of the queue buffer (3), passes through an OR circuit 72, and outputs the logical sum of this signal and the lock signal 5LOC of the system bus, and the AND circuit A signal obtained by performing an AND operation with a signal obtained by inverting the output of FF 79 is synchronized with an FF 74 and outputted as a system bus lock signal 5LOC.

Therefore, according to the circuit shown in FIG. 4, after the local bus lock signal is negated, the bus interface circuit BI
In the next cycle after F asserts the transfer end signal CPT, the system bus lock signal 5LOC can be negated.

FIG. 5 explains the operation of T&S control according to the embodiment of FIG. 4.

In the example of FIG. 5, since T&5tlIIIll is performed, a read operation is performed first, and then a write operation is performed.

(2) The read operation is the same as in the embodiment shown in FIG.

■ Next, during the write operation, the microprocessor μP asserts the transfer start signal BS, outputs the address and data, and when the output ends, the transfer end signal CP is output.
T is asserted and the local bus lock signal LOC is negated.

■ In this state, the bus interface circuit BIF asserts the request signal REQI without negating the lock signal 5LOC of the system bus, and connects the common memory C
When receiving the acknowledge signal ACK1 from M, it asserts the transfer start signal SBS on the system bus and transfers the command C and address A onto the system bus. At the end of the transfer, after asserting the transfer end signal CPT,
Negate system bus lock signal 5LOC.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of central processing units and a common memory are connected to the system bus, and each central processing unit is connected to the system bus via a bus interface circuit connected via a local bus. In a multiprocessor system connected to a computer, when lock transfer is performed with the bus interface circuit set to the constant mode, it can be executed without setting the constant mode to the non-constant mode in advance.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are diagrams showing the basic configuration of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the operation of T&5IiJIl according to the embodiment of FIG. Diagram to explain,
FIG. 4 is a diagram showing another embodiment of the present invention, FIG. 5 is a diagram explaining the operation of T&S@ll according to the embodiment of FIG. 4, and FIG.
The figure is a diagram illustrating the configuration of a multiprocessor system, FIG. 7 is a diagram illustrating the configuration of each central processing unit, FIG. 8 is a diagram illustrating the connection between the bus interface circuit and the bus arbiter, and FIG. 9 is a diagram without exceptions. FIG. 10 is a diagram explaining the operation of the bus interface circuit in the mode, and FIG.
Figure 1 shows the format of system bus commands and answers, Figure 12 shows the configuration of the bus interface circuit, Figure 13 shows the configuration of the local bus reception control section, and Figure 14 shows the conventional A diagram showing the configuration of the DC@@ section,
FIG. 15 is a diagram showing the configuration of a FIFO control section, FIG. 16 is a diagram showing the configuration of a transmission control section, and FIG. 17 is a diagram showing the configuration of a conventional lock line control section. μP is a processor, BIF is a bus interface circuit,
1 is a non-intermittent mode operation function, 2 is an intermittent mode operation function, 3 is a system bus slot transfer function, 4 is a lock transfer control function, 5 is a lock transfer completion detection function, 6 is a lock transfer termination function, 11 is a system Bus 12 is a local bus.

Claims (2)

[Claims] (1) Each bus interface circuit (BIF) in a multiprocessor system in which each processor (μP) is connected to the system bus (11) via a bus interface circuit (BIF) connected via a local bus (12).
) forwards accesses received from the local bus (12) to the system bus (11) and releases the local bus (12) when access to the system bus (11) is completed; ), and a disconnection mode operation function (2) that immediately releases the local bus (12) when an access is received from the local bus (12) and then transfers the access to the system bus (11), and When (12) has a system bus lock transfer function (3) that detects when the lock transfer state is entered and transfers the lock to the system bus (11), the above-mentioned disconnection mode operation function (2) is effective. When the access received from the local bus (12) is due to lock transfer, the access is transferred to the system bus (11) without releasing the local bus (12) when the access is received. ) A lock transfer method is characterized in that it includes a lock transfer control function (4) that releases the local bus (12) after access to the local bus (12) is completed. (2) Each bus interface circuit (BIF) in a multiprocessor system in which each processor (μP) is connected to the system bus (11) via a bus interface circuit (BIF) connected via a local bus (12).
) forwards accesses received from the local bus (12) to the system bus (11) and releases the local bus (12) when access to the system bus (11) is completed; ), and a disconnection mode operation function (2) that immediately releases the local bus (12) when an access is received from the local bus (12) and then transfers the access to the system bus (11), and (12) has a system bus lock transfer function (3) that detects when it is in a lock transfer state and transfers the lock to the system bus (11), the lock transfer of the local bus (12) is completed. a lock transfer completion detection function (5) that detects the completion of the lock transfer; and a lock transfer termination function (5) that terminates the locked state of the system bus (11) when access to the system bus (11) is completed after detecting the completion of the lock transfer. 6) A lock transfer method characterized by providing the following.