JPH0420544B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a CCITT Recommendation V.33 modem, in order to reduce the number of interface signals with the outside, rate sequence bit information is exchanged using SD signals and RD signals. In order to reduce the burden on external control, the signals received by the receiving section are compared eight times.

[Industrial application field]

The present invention relates to a rate sequence of a modem, such as a V.33 modem, which includes a rate sequence in a synchronization signal.

Conventional modems have the disadvantage that the device configuration is complicated because many wires are used to connect the control section and the transmitting section or the receiving section, and the burden of external control is large.
This improvement was required.

[Conventional technology]

CCITT Recommendation V.33 modem for data transmission is
This is a modem that uses QAM modulation and performs point-to-point communication using a 4-wire dedicated line.

Moreover, the communication speed and multiplexing mode can be set externally, and the speed is 12Kbit/s and 14.4Kbit/s.
It is possible to take two communication speeds.

Also, even if the communication speed is 14.4Kbit/s, for example, you can connect two terminals with a communication speed of 7.2Kbit/s to multiplex and transmit at a communication speed of 14.4Kbit/s, or 4.8Kbit/s. It is also possible to connect and multiplex three terminals with a communication speed of 14.4 Kbit/s and transmit data at a communication speed of 14.4 Kbit/s.

In this way, the V.33 modem is a device whose communication speed and multiplexing mode can be set and used externally.

FIG. 2 is a diagram illustrating a training signal for a V.33 modem. The same symbols represent the same objects throughout all the figures below.

For this reason, in the V.33 type modem, at the start of communication, a training signal shown in FIG. 2 is sent from the transmitting side to the receiving side to notify the communication speed and multiplexing mode.

In the segment SEG1 shown in FIG. 2, an alternating signal (ABAB repeating signal) is sent out, and its communication speed is 2400 bit/s.

In segment SEG2, scrambled signals A, B, C, and D are sent out at 4800 bit/s, and are used for equalizer adjustment on the receiving side.

In segment SEG3, a rate sequence signal is also transmitted at 4800 bit/s, and the receiving side receives this signal, identifies the communication speed and multiplexing mode, and takes this preparation mode.

In segment SEG4, a signal is sent out at the communication speed and multiplexing mode specified in segment SEG3.

The above training signal is sent out over about 1.3 seconds, and when it is finished, data transmission begins.

The present invention deals with the rate sequence of segment SEG3.

The purpose of segment SEG3 is as described above, but for this purpose a 16-bit signal is sent eight times in succession, and this 16-bit signal contains information specifying the communication speed and multiplexing mode. 16 on the receiving side
Receives 16-bit signals 8 times in a row, compares them, receives accurate 16-bit signals, and adjusts the state of the device to match the specified communication speed and multiplexing mode based on this received information. and segment as desired.
After receiving SEG4 and making more detailed adjustments, data reception begins.

As can be seen from the above explanation, in V.33 type modems, when starting the communication speed, it is necessary on the transmitting side to change the bit information transmitted by external setting information (communication speed, multiplexing mode, etc.). On the receiving side, it is necessary to set the communication speed, multiplexing mode, etc. based on the rate sequence bit information (16-bit signal) from the opposing modem.

Therefore, it is necessary to exchange bit information of the rate sequence between the transmitter and the controller and between the receiver and the controller.

FIG. 3 is a diagram showing an example of a conventional rate sequence control method.

In the figure, 1 is a control section, 2 is a multiplexing/distributing section, 3 is a transmitting section, 4 is a receiving section, 5 is a switch, and 6 and 7 are terminals, respectively.

Let's take as an example the case where terminal 6 and terminal 7, which have a communication speed of 7.2 Kbit/s, are connected to this modem, and these are multiplexed and sent to the opposing modem at a communication speed of 14.4 Kbit/s. explain.

First, setting information (normal speed and multiplexing mode = 16-bit signal) is set in the control section 1. The control unit 1 sends a multiplexing mode signal to the multiplexing/distributing unit 2,
The multiplexing/distributing unit 2 is set to convert two channels having a communication speed of 7.2 Kbit/s into one channel having a communication speed of 14.4 Kbit/s.

Next, the control section 1 controls the switch 5 to transmit the signal to the transmitting section 3.
The multiplexing/distributing section 2 is separated from the multiplexing/distributing section 2, and the aforementioned 16-bit signal is sent to the transmitting section 3 in parallel format using 16 transmission bit information lines ( _x1 to _X16 ).

When the transmitter 3 receives this signal, it converts this signal into a serial signal and transmits it eight times at 4800 bit/s.
This is segment SEG3 mentioned above.

After the transmitting section 3 continues to send out segment SEG4, the control section 1 controls the switch 5 again to connect the transmitting section 3 and the multiplexing/distributing section 2, and sends the multiplexed transmission data SD from the transmitting section 3 to the opposing modem. to
Sends at a communication speed of 14.4Kbit/s. Furthermore, control section 1
Control from the transmitter 3 is transmitted via the control signal line b.

In the modem on the receiving side, the receiving section 4
After receiving and comparing SEG3 (8 times of 16-bit signals) and converting the accurate 16-bit signals into parallel signals, the 16 received bit information lines (y ₁ to y ₁₆ )
The information is transmitted to the control unit 1 via the . The control unit 1 sends a multiplexing mode signal to the multiplexing/distributing unit 2, and the multiplexing/distributing unit 2 transmits a communication speed of 14.4 Kbit/s to one channel.
Set to distribute to 2 channels with communication speed of 7.2Kbit/s. As a result, the received data RD having a communication speed of 14.4 Kbit/s sent via the signal line c is sent to the multiplexing/distributing section 2.
The signal is separated into two channels having a communication speed of 7.2 Kbit/s and output to terminal 6 and terminal 7, respectively. Note that a control signal from the control section 1 to the reception section 4 is transmitted via a control signal line d.

[Problem that the invention seeks to solve]

However, in the conventional system, between the control section 1 and the transmission section 3, there are 16 sets of transmission bit information lines (x ₁ to x ₁₆ ), 1 set of signal lines a, and 1 set of control signal lines B, for a total of 18 sets. A wire is required between the control section 1 and the reception section 4 as well.
The disadvantage was that 18 sets of wires were required, so a total of 36 sets of wires had to be used.

[Means for solving problems]

The above problem is solved by connecting the control section 1a and the transmitting section 3a with three sets of wires a, b, and e as shown in FIG.
The line a is connected to the serial transmission data signal line (SD signal line) to the transmitter 3a via the switch 5,
The control section 1a and the reception section 4a are connected by three sets of lines c, d and f, and the sixth line c is connected to a serial reception data signal line (RD signal line) from the reception section 4a,
On the transmitting side, the control unit 1a connects to the transmitting unit 3a via line b.
and the third line a and the transmitter 3a based on the synchronization signal sent from the transmitter 3a via the line e.
The switch 5 is controlled so that the SD signal line of the transmitter 3a is connected to the transmitter 3a, and 16-bit information specifying the communication speed and multiplexing mode is sent to the transmitter 3a in the form of a serial signal via the line a. transmits the 16-bit information 8 times in a row, and on the receiving side, the controller 1a controls the receiver 4a via the line d, and the receiver 4a receives the 16-bit information 8 times in a row and compares them with each other to ensure accuracy. This problem is solved by determining the exact 16-bit information and sending the correct 16-bit information to the control unit 1a in the form of a synchronization signal via the line f and in the form of a serial signal via the line c.

[Effect]

According to the present invention, the number of lines between the control section and the transmitting section or the receiving section is significantly reduced, so that the interface signal is simplified and the equipment configuration is simplified.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a rate sequence control method according to the present invention.

In the figure, 1a is a control section, 3a is a transmitting section, 4a is a receiving section, and 1x is a P/S conversion circuit.

In the present invention, the 16 sets of transmission bit information lines connecting the conventional control section and the transmission section are abolished, and the signal line a
is used to send the information of segment SEG3 in serial format to the transmitter via switch 5, and for this purpose one new synchronization signal line e is added. Furthermore, the control unit 1a according to the present invention has 16
A P/S conversion circuit 1x with a function of converting bit setting information into serial format is added.

Every time one synchronization signal is sent from the transmitter 3a, the controller 1a drives the P/S conversion circuit 1x, sends out 16-bit information once in serial format using the signal line a, and transmits it. The unit 3a repeatedly sends the received 16-bit information eight times to the opposite modem.

On the receiving side, when the receiving unit 4a receives the synchronization signal once, it notifies the control unit 1a, and also receives eight consecutive 16-bit information, compares the eight 16-bit information, and determines whether the synchronization signal is correct and correct. This accurate 16-bit information is transmitted once to the control unit 1a using the signal line c.

The control unit 1a receives accurate information via the signal line c.
Based on the 16-bit information, the multiplexing/distributing section 2 is controlled and set to a predetermined state, and ready to receive the received data RD.

When 16-bit information is exchanged using signal lines a and c in this way, the transmitter 3a and the receiver 4a are transmitting or receiving a synchronization signal, and at this time, the transmit data SD and the receive Data RD is invalid.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the number of lines between the control unit and the transmitting unit or the receiving unit is significantly reduced, which simplifies the interface signal and simplifies the equipment configuration. There is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of a rate sequence control method according to the present invention. FIG. 2 is a diagram illustrating a training signal for a V.33 modem.
FIG. 3 is a diagram showing an example of a conventional rate sequence control method. In the figure, 1 is a control section, 2 is a multiplexing/distributing section, 3 is a transmitting section, 4 is a receiving section, 5 is a switch, 6 and 7 are respective terminals, 1a is a control section, 3a is a transmitting section, and 4a is a receiving section 1x is a P/S conversion circuit.

Claims (1)

[Claims] 1. In a data communication modem, a control section 1a that controls a setting import operation and a transmitting section 3a including a modulation section are connected by three sets of wires a, b, and e, and a third The line a is a serial transmission data signal line (SD signal line) to the transmitter 3a via the switch 5.
The control section 1a and the receiving section 4a including the demodulating section are connected by three sets of lines c, d, and f, and the sixth line c is a serial reception data signal line (RD signal) from the receiving section 4a. On the transmitting side, the control unit 1a controls the transmitting unit 3a via the first line b, and receives the synchronization signal sent from the transmitting unit 3a via the second line e. Based on the third line a and the transmitter 3a
controls the switch 5 so that the SD signal line is connected to the transmitter 3a, and sends 16-bit information specifying the communication speed and multiplexing mode to the transmitter 3a in the form of a serial signal via the third line a; The transmitting section 3a sends out the information, and on the receiving side, the control section 1a controls the receiving section 4a via a fourth line d, and the receiving section 4a continuously receives the information and communicates with each other. A comparison is made to obtain the accurate information, and the fifth line f
A rate sequence control method characterized in that a synchronization signal is sent to the control unit 1a in the form of a serial signal via a sixth line c.