JPH04206095A - Method for erasing nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of erasing a nonvolatile semiconductor memory device, particularly a flash EEFROM that can be electrically erased all at once.

[Conventional technology]

Figure 3 is from the IEEE Journal of 5oli
d-5tate Circuits, Vol, 23. No
,5,0ctober 1157-116 in 1988
A block diagram of the conventional FLASH EEFROM shown on page 3 is shown. There is a Y gate (2) around the memory play (1).
), a source line switch (3), an X decoder (4), and a Y decoder (5). An address register (6) is connected to the X decoder (4) and the Y decoder (5),
An address signal input from the outside is input.

The memory array (1) is connected to the input data register (write circuit) + 7L sense amplifier (
8) is connected. The input data register (7) and sense amplifier (8) are connected to the input/output buffer (9).

In addition, a program voltage generation circuit α [, a verify voltage generation port 1s (11) is provided, which generates a voltage different from the externally supplied Vce and Vpp, and generates a voltage different from the Y gate 1
2) Supplied to the X decoder (4), etc. A command register (12) and a command register (13) are used to set the operating mode according to data input from the outside. Furthermore, an input signal buffer (14) is provided, which receives external control signals WE, CE.

■ is connected.

FIG. 4 shows a cross-sectional view of the memory cell of FIG. 3.

The memory cell includes a floating gate (16), a control gate (17), a source diffusion region (18), and a drain diffusion region (19) formed on a semiconductor substrate (15).
It consists of floating game) (16)
, the oxide film thickness between the semiconductor substrates (15) is thin < (100
This enables electrons to move to the floating gate (16) using the tunneling phenomenon.

The operation of the memory cell is as follows. During programming, a program voltage of about 6.5V is applied to the drain (19), and Vpp (12V) is applied to the control gate (17).
) is applied and the source (18) is grounded. Therefore, the memory cell turns on and current flows. At this time, avalanche breakdown occurs near the drain (19) and electron-hole pairs are generated. The hole pairs flow through the semiconductor substrate (15) to the ground potential, and the electrons flow toward the channel and into the north (18). However, some electrons are accelerated by the electric field between the floating gate (16) and the drain (19) and are injected into the floating gate (16).

Thus 1. Increase the threshold of memory cells. This is defined as storing information "0". On the other hand, erasing drains (1
9) is opened, the control gate (17) is grounded, and VPP is applied to the source (18). A tunneling phenomenon occurs due to the electric field between the source (18) and the floating gate (16), and the floating gate) (1
6) Withdrawal of electrons inside occurs.

Thus, the threshold value of the memory cell is lowered. This is defined as storing information "1".

FIG. 5 shows a circuit diagram of the write circuit of the memory array of FIG. The memory cell has its drain (19) connected to the bit line (24) and its control gate (17) connected to the word il.
l (connected to 251. Word line (25) is connected to
The bit line (24) is connected to the I 709 (27) via a Y gate transistor (2) whose gate receives the output of the Y decoder (5). 1. The 10th line (27) has a sense amplifier (8
) A write circuit (7) is connected, and a source line (28) is connected to a source line switch (3).

Next, the operation will be explained.

The case where writing is performed in the memory cells surrounded by dotted lines in FIG. 5 will be described. The write circuit (7) is activated according to data input from the outside, and the I10 line (27)
A programming voltage is supplied to the At the same time, the address signal selects Y gate (26) word i@ (25) through Y decoder (5) and X decoder (4), and VPP
is applied. Source il! (2g) is grounded by the source line switch (3) during programming. In this way, current flows through only one cell in the figure, hot electrons are generated, and its threshold voltage increases.

Erasing is performed as follows. First, the X decoder (4) Y
Decoder (5) is deactivated and all memory cells are deselected. That is, the control gate (17) of each memory cell is grounded, the drain (19) is left open, and a high voltage is supplied to the source line (28) by the source line switch (3). In this way, the threshold value of the memory cell is shifted to the lower side due to the tunneling phenomenon. Since the source line (28) is common, all memory cells are erased at once.

Next, the read operation will be explained. Similar to writing, reading of the memory cells surrounded by dotted lines in FIG. 5 will be described. First, the address signal is sent to the Y decoder (5)
Decoded by the decoder (4), the selected Y gate (26) and word line (25) become "H". At this time, the source line (28) is grounded by the source line switch (3). In this way, if the memory cell is written and its threshold value is high, even if H'' is applied to the control gate (17) of the memory cell by the word line (25), the memory cell will not turn on, and bit II (24) will not turn on. ) to the source line (28).On the other hand, when the memory cell is being erased, the memory cell is turned on, so current flows from the bit line (24) to the source line (28). The sense amplifier (8) detects whether or not current flows through the memory cell, and reads the read data "1".
Get “0”.

Now, in EEPROM, erasing is done by ultraviolet irradiation, so once the floating gate becomes electrically neutral, no more electrons are extracted from the floating gate, and the threshold value of the memory transistor does not fall below about IV. . On the other hand, when electrons are extracted using the tunneling phenomenon, electrons may be excessively extracted from the floating gate, and the floating gate may become positively charged. This phenomenon is called over-erasure (or over-erasure). Since the threshold value of the memory transistor becomes negative, subsequent reading and writing will be hindered. That is, even if the level applied to the control gate of the memory transistor is "L" when the word line is not selected and the level of the word line is "L" at the time of reading,
Since current flows from the bit line through the memory transistor, even if the memory cell on the same bit line that is attempting to read is in the write state and has a high threshold value, “
1'' is read.Also, even during writing, leakage current flows through over-erased memory cells, which deteriorates the writing characteristics and even makes writing impossible.For this reason, reading after erasing is performed. (This method is used to check whether the erase has been performed correctly (this is called erase verify), and if there are bits that are not erased, perform the erase again to prevent unnecessary erase pulses from being applied to the memory cells. Figure 6 is a flowchart of erasing and programming including such a verify operation, and Figure 7 shows a timing waveform diagram of each of them.Using these diagrams and Figure 3, erase and program Each step of programming and programming will now be described. In a conventional flash EEPROM, mode setting for erasing and programming is performed by a combination of input data. In other words, mode setting is performed by input data at the rising edge of WT.

First, the case of a program will be explained. At the beginning, V
ec and Vpp are started up (step Sl), and then W
E is brought down. Thereafter, at the rising edge of WE, the input data (40H) is latched into the command register (12) (step S2). Thereafter, the input data is decoded by the command decoder (13), and the operation mode becomes the program mode. Subsequently, WE is brought down again, and the address from the outside is latched into the address register (6).
Data is latched into the write circuit (7) at the rising edge of WE. (Step 33). Next, a program pulse is generated by the program voltage generation circuit (10) and applied to the X decoder (4) and Y decoder (5). Programming is then performed as previously described (step 54).
).

Next, when WE falls, and when WT rises, the input data (COH) is latched into the command register (12), and the operating mode becomes program verify mode (
Step S5). At this time, a program verify voltage (~7.OV) is generated inside the chip by the erase/program verify voltage generation circuit (11) and applied to the X decoder (4) and the Y decoder (5). Since the voltage applied to the control gate (17) of the memory cell is higher than that during normal reading (5V), memory cells with insufficient writing are more likely to be turned on, and writing defects can be detected more reliably. Next, reading is performed (step S7), and writing data is confirmed (step S7).
8). At this time, if the writing is insufficient, the writing is repeated further. If writing has been performed, the operation mode is set to read mode (step 39) and the program is terminated.

Next, the case of erasure will be explained. First, Vec,
Vpp is turned on and vignetting occurs (step 510), and then "0" is written to all bits using the program flow described above (step 511).

This is because when an erased memory cell is further erased, the memory cell is overerased. Next, WE falls, and an erase command (20H) is input at the subsequent rise of WT (step 512). Next, WT is brought down again, and an erase command (20H) is input at the rising edge of WE (step 813). At this time, an erase pulse is generated inside the chip, and the source line switch continues until the falling edge of WE. (3) to the source (1g) of the memory cell.
P is applied. (Step 514). The address is also latched at this falling edge. At the rising edge of WE, the erase verify command (AOH) is latched, and the operation mode becomes the erase verify mode (step 515).

At this time, erase/program verify voltage generation circuit (1
1), an erase verify voltage (~3.2V) is generated and applied to the X decoder (4) and the X decoder (5). Since the voltage applied to the memory cell control gate (17) is lower than that during normal reading (5V), it becomes difficult to turn on memory cells that are insufficiently erased, making it possible to detect erase defects more reliably. . Next, reading is performed (step 316), and the erased data is confirmed. At this time, if the erasure is not sufficient, the erasure is repeated.

If erasure has been performed, the address is incremented (
Step 517), verify the erased data at the next address. If the verified address is the last address (step 518), the operation mode is set to read mode (step 519) and erasing is completed.

[Problem to be solved by the invention]

The conventional flash EEFROM erasing method was structured as described above, so before erasing all bits, all bits were
Since '0' is written, the VTH of the memory cell before batch erasing varies between bits that have already been written and bits that are erased, and as a result, the VTH of the memory cell after batch erasing also varies. There was a problem with this.

This invention was made to solve the above-mentioned problems, and aims to suppress variations in VTH of memory cells before batch erasing, and further suppress VT)I of memory cells after batch erasing. .

[Means to solve the problem]

The flash EEPROM erasing method according to the present invention is as follows:
The stored information is read out, its inverted information is written, and then erased all at once.

[Effect]

The flash EEFROM erasing method in this invention writes "o" only to the erased bits by writing inverted information of the stored information, and erases the already written bits and the erased bits all at once. Suppress variations in VT)l of the previous memory cell.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
FIG. 1(a) is a flowchart for reading out stored information and writing its inverted information, which is an embodiment of the present invention.
b) is a flowchart of erasing which is an embodiment of the present invention, and FIG. 2 is a timing waveform diagram of FIG. 1(a).

The erasing method will be explained using FIGS. 1 and 2. First, Vee, Vpp are launched (step 510). Next, WE is lowered, and when WE rises, a read command (OOH) is input (step 520), and reading is performed (step 521). Next, WE is brought down, and a program command (40H) is input at the subsequent rise of WE (step S2). Next W
The address is input at the falling edge of the clock, and the inverted information of the read information is input at the rising edge (step S3). If programming has been completed in program verify (step 36), the address is incremented and the next address is read and programmed. If the verified address is the last address, the operation mode is set to read mode, the program is ended, and erasing is performed (step S12 onwards).

In the above embodiment, the case of batch erasing was explained, but a flash with sector erasing function: LEEPRO
A similar erasing method can be applied to M as well.

〔Effect of the invention〕

As described above, according to the present invention, "0" is written only to the bits in the erased state by writing inverted information of the stored information, so that the bits in the already written state and the bits in the erased state With this, it is possible to suppress the variation in VTH of memory cells before batch erasing, and the erasing time for each bit becomes uniform, and while the bits with a longer erasing time are being erased, the bits with a shorter erasing time are over-erased. This has the effect of making it more difficult.

[Brief explanation of the drawing]

FIG. 1(a) is a flowchart for reading out stored information in a nonvolatile semiconductor memory device and writing inverted information thereof, which is an embodiment of the present invention, and FIG. 1(b) is an embodiment of the present invention. Similarly, a flowchart diagram for erasing, FIG. 2 is a timing waveform diagram of FIG. 1(a), FIG. 3 is a block diagram of a conventional flash EEPROM, and FIG. 4 is a cross-sectional view of the memory cell of FIG. 3. 5 is a circuit diagram of the write circuit of the memory array shown in FIG. 3, and FIGS. Figure 7 (a) (b) is the same as Figure 6 (a) (b)
This is a timing diagram of the cost.

Claims (1)

[Claims] A plurality of memory cells including non-volatile memory transistors arranged in an array at least in the row and column directions and capable of electrically writing and erasing information, and decoding externally input address signals, Equipped with an X decoder and a Y decoder that select the direction, and a sense amplifier that determines whether the information stored in the memory cell is "1" or "0", it is possible to write and erase information electrically. 1. A method for erasing a nonvolatile semiconductor memory device, which comprises reading out stored information, writing inverted information therein, and then erasing it all at once.