JPH04207263A - mark detection device - Google Patents

Abstract

PURPOSE:To detect the markers in the part shaded by markers by detecting a 1st mark area by synthesis with the 2nd mark area detection signals existing in the 1st mark area. CONSTITUTION:The mark assigned on an original via a CCD, etc., is detected by optical scanning and is processed in the mark area detections section constituted of the 1st mark area detecting section and the 2nd mark area detecting section. The 1st mark area is detected with good accuracy by the synthesis of the detection signals by the 1st mark outer and inner position detecting sections 151, 160, the 1st mark outer, inner and inner area detecting sections 152, 161 and the detection signals by the 2nd mark outer and inner area detecting sections 155, 164 of the 2nd mark existing on the inner side of the 1st mark by the 2nd mark area detecting section in the 1st mark area detecting section. The marks are detected without erroneous detection of double circular marks, etc., even if the marks exists in recessed parts when the marks are recessed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mark detection device, and more particularly to a mark detection device that detects a mark attached to a desired area of a document for various image processing purposes.

[Prior Art] In various image forming devices such as copying machines and facsimile machines, by attaching special marks to documents, it is possible to edit images or read images accurately without requiring the operator's effort. The technology was developed 1 for example in JP-A-64
This method is disclosed in Japanese Patent Application Laid-open No. 19871 and Japanese Patent Application Laid-open No. 1-170163.

This type of technology is used to detect marks placed on documents, but in conventional mark detection, the density and width of the mark are detected, and a preset constant value is detected to be recognized as a mark. Determining whether it is within the range.

In this type of apparatus, the mark width is detected assuming that the document is the same size as the original.

FIGS. 35(a) and 35(b) are explanatory diagrams of the conventional mark detection operation, and even if the mark detection reference width Ws is set at a magnification of 1 as shown in FIG. 35(a), the magnification is 1/ 2, the mark width is reduced and may not be detected as a mark. Furthermore, even if the density is the same as the mark density, even line information that is too narrow to be detected as a mark will be detected as a mark at a magnification of 2, as shown in FIG. 2B.

[Problems to be Solved by the Invention] By the way, in conventional mark area detection, it has not been possible to detect marks within the markers engraved on the scanning line.

For example, as shown in Fig. 37, there is a part (
(shown with diagonal lines) is considered a marker area. Therefore, there is a concave portion on the sub-scanning side, and there is a problem that the image information in the concave portion may disappear or remain when editing, such as erasing inside the mark or deleting outside the marker.

Furthermore, as shown in FIG. 38, the area (indicated by diagonal lines) that cannot be seen due to the shadow of the marker from any of the y, xl, and x2 directions is regarded as the marker area.

Further, as shown in FIG. 39, since the marker spacing within the marker cannot be detected, complex marker editing cannot be performed.

The present invention has been made in view of the above-mentioned problems of the prior art, and is intended to solve the problems.The purpose of the present invention is to enable detection of markers in areas shaded by markers, and to enable complex mark area editing. The object of the present invention is to provide a mark detection device that provides the following.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a reading means for reading an original image and generating image information, a specifying means for specifying a desired area of the original by a mark, and a designated area. a first signal generating means for generating a mark reading signal; a second detecting means for detecting an area inside the mark; and detecting a mark within the area inside the mark obtained by the second detecting means. a second signal generating means for generating a signal;
a third detection means for detecting an area outside the mark in the main scanning direction using a signal obtained from the signal generation means; a fourth detection means for detecting an area inside the mark;
a second synthesizing means for synthesizing the mark inner signal obtained from the detection means and the mark outer signal obtained from the third detection means; and a mark reading signal obtained from the first signal generating means. and a first detection means for detecting an area outside the mark in the main scanning direction using the composite signal obtained by the second composition means; The present invention is configured to include a first synthesizing means for synthesizing the signals inside the mark obtained from the detecting means of the document. a first signal generating means for generating a reading signal of the mark area designated by the specifying means, a first storage means for storing the detected position information, and a first storage means for storing the detected position information. a control means for controlling reading and writing of the mark; a second signal generation means for generating a signal based on the position information read by the first storage means; and a position of the outer tip of the mark is detected by the first signal generation means. a second detection means, the second detection means;
A third signal generating means generates an outside area signal of the mark using the signals obtained from the detecting means and the second signal generating means, and the first signal generating means generates positional information of the inner rear edge of the mark. A third detection means for detecting, a second storage means for storing the third detected position information, a control means for controlling reading and writing of the second storage means, and a position read from the second storage means. a fourth signal generating means for generating a signal based on the information; a fourth detecting means for detecting the inner tip position information of the mark by the first signal generating means; the fourth detecting means and the fourth signal generating means; The present invention further includes a fifth signal generating means for generating an inner area signal of the mark using the signal obtained by the means.

[Operation] By using the above means, in mark area detection, the detection of the first mark area is performed using a composite signal with the second mark area detection signal within the first mark area. 1. On the sub-scanning side. Even if the mark is concave,
The marked area can be detected correctly. Therefore, the character information in the recessed part is not erased in the inside-marker erasing mode, and the character information in the recessed part does not remain in the outside-marker erasing mode.

2. Furthermore, even if there is a mark inside the recess,
Both the mark area of the recess and the mark area inside the recess can be detected correctly.

3. Even if there are multiple marks, each mark can be detected, so it is possible to extract the inner line information when erasing inside the marker, and the outer line information when erasing outside the marker, making it possible to detect complex marks. Area editing becomes possible.

Further, since the above means detects the inner area of the first mark area, it is possible to detect the second mark area within the first mark area. Therefore, in mark area editing, the same effect as described above is possible.

[Example code] Embodiments of the present invention will be described below with reference to the drawings.

First, an image processing apparatus to which an embodiment of the present invention is applied will be described.

Figure 2 shows the document, combination lens, and C in the image processing device.
3 is a diagram showing a CD line sensor 21, and FIG. 3 is a block diagram showing the configuration of an image processing device to which a mark detection device according to an embodiment of the present invention is applied.

In FIG. 3, 4 is a scanner section, and this scanner section 4
As shown in FIG. 2, an image of the reading line Q of the original 1 is focused on the CCD line sensor 3 via the coupling lens 2, and the relative position between the original 1 and the CCD line sensor 3 in the Y direction is While updating the reading line by mechanically shifting the position = (sub-scanning), each line is moved from left to right in the input direction by 40
Read at a density of 0 dpi (=16 pixels/'') (main scan)
.

The read signal becomes an analog signal having an amplitude corresponding to the density of each pixel. S is a video processing circuit which A/D converts the read signal f1, performs background removal processing, shininess correction processing, MTF correction processing, etc. to produce 8-bit (256 gradation) image data f2 (the higher the value, the higher the This is a circuit that generates high-density). Reference numeral 6 denotes a data processing control unit, and this data processing control unit 6 reads the data and sets the black pixel to ``1'' = H level and the white pixel to 110.
It is binarized as 11°L level, and the designated area is extracted (trimmed), erased (masked), etc.
This is to generate write data f3.

8 modulates the laser beam with A○ (1: recording, O: non-recording)
This is a laser printer that prints out images on recording paper.

In the above image processing device, the control device for controlling each of these components, the scanner section 4, the video processing circuit 5, and the laser beam printer 8 are known technologies.
2. The data processing control unit 6 detects a mark in a predetermined density range written on the document l or an area surrounded by the mark, and Based on this, trimming, masking, etc. are performed on the original.

In this embodiment, a mark using a color felt pen (hereinafter referred to as a color mark) is used as a mark for a predetermined density range.
Assume that This is because color felt-tip pens are already available in various densities, and this makes it easy to mark a predetermined density range, which is advantageous in practice.

Fig. 1 is a block diagram showing the configuration of the main parts of the embodiment, Fig. 4 is a characteristic diagram of image density information, Fig. 5 is a circuit diagram of the mark level detection section of the embodiment, and Fig. 6 is noise on marks. FIG. 7 is a circuit diagram of the mark noise removal section of the embodiment.

In FIG. 1, reference numeral 50 denotes a mark density level detection unit, which extracts marks by utilizing the characteristic that the marks have a constant density.As shown in FIG. The image within THI is set as the first candidate for the mark. In other words, the background of an image is usually on the white side in terms of density, and line information such as a single character is on the black side in terms of density.

The above determination method is used because the mark exists in the intermediate density area.

In the mark level detection section of the embodiment shown in FIG. 5, a comparator 52 compares the mark upper limit threshold level TH2 and the input image, and if the input image density is lower than the threshold level TH2, the input image is a mark or background. The mark lower limit threshold level THI is compared with the input image by a comparator 51, and if the density of the input image is greater than the threshold level THI, the input image is determined to be a mark or a character, Based on these judgments, the AND circuit 53 determines the mark signal.

However, there is also information with a light density such as letters, and if the M has a density similar to that of a mark, the mark level detection unit 50 treats it as a mark, so erroneous detection is prevented as described below. . The level detection section 50 also outputs the mark lower limit threshold level and the output of a comparator 51 to which input data is input, for use in a mark connection section to be described later.

In FIG. 1, 60 is a mark noise removal section, and this mark noise removal section 60 has a function of removing image noise using the signal a obtained from the above-mentioned mark level detection section 50.

Generally, when specifying a mark with a marker pen or the like, noise may occur here and there even if the mark density is uniform. Although this noise varies depending on the document, there are cases where the density becomes white and the density decreases, and cases where the density becomes black and the density increases, and the mark signal is divided by this noise.

This state is shown in Figure 6. As shown in the figure, the signal a after detecting the mark level is divided by white noise and black noise, so it is necessary to remove the noise signal superimposed on the mark. Is required. Figure 7 shows 1
This is a mark noise removal unit used to remove pixel noise.If the periphery (X in the figure) of the center (C in the figure) in a 3×3 matrix is at the mark level, ○
Regardless of the mark level, ○ is set as the mark level, and if even one of the × is not at the mark level, ○ is left as the image signal a, thereby removing 1 pixel of noise.

Therefore, in order to align the images in a 3×3 matrix on the same time axis, the memory 61 is used to
Gather the Ωine data. In FIG. 7, this memory 61 uses a FIFO (first-in-fast 0UT) memory.

Since the FIF○ memory is well known, it will not be explained. The data of 3Ωine is latched by the FIFO memory 61 in the main scanning direction by flip-flops (hereinafter referred to as F/F) 62 and 63, and the data of the signal a in the 3×3 matrix is aligned on the same time axis. .

After this, the signal of only the × is input to the AND circuit 64, and if the signal is H, it is determined that all the × are at the mark level, and the selector 65 selects the H signal of A manually to set it to the mark level, Even if X is 1, when it is not at the mark level, the output of the AND circuit 64 becomes L, so the selector 65 selects and outputs the L signal.

Here, the reason why 1 pixel noise is removed is because noise occurs in the example, and the most common one is 1 pixel noise.
This is because the noise is xel noise, and depending on the frequency of noise occurrence, the noise area may be expanded to 2pixel or 3pixel. Furthermore, in order to simplify the hardware,
It is also possible to remove noise only in the main scanning direction or only in the sub-scanning direction. Furthermore, in a system where the probability of noise occurrence is low, it is possible to have a configuration in which this mark noise removal section is not included.

FIG. 8 is a circuit diagram of the blocking circuit section of the embodiment, FIG. 9 is a timing chart showing the operation of the blocking circuit section of the embodiment, and FIG. 10 is a block diagram showing the configuration of the mark width detection section of the embodiment. It is.

The blocking circuit section 70 shown in FIG. 1 described above has a function of blocking the output signal C of the mark noise removing section 60 into 2×2 blocks. This blocking circuit section 7o prevents the paper from detecting a mark density portion other than the area marked with the marker pen and the detected area. For example, if there is a small stain on the document, the blocking circuit 70 divides the document into blocks so that the stain is not determined to be a mark even if the level of the stain is at the mark density level. Furthermore, in this embodiment, by forming blocks, the amount of information to be processed is reduced to 1/4, since 2×2 blocks (2 in the main scanning direction and 2 in the sub-scanning direction) are processed as one unit, which simplifies the hardware configuration. And cost reduction is also achieved.

In FIG. 8, 71 and 72 are FIFO memories, and the memory 71 aligns the data of 2Ωins on the same time axis, and the memory 72 aligns the data of 2Qi by 2flines.
The same 2Qine data is output in the ne step. This control inputs the line effective reading width signal LGATE to the read/write terminal of the memory 71, inputs the signal obtained by dividing this line effective reading signal LGATE by two to the FIFO write terminal of the memory 72, and inputs the signal to the read terminal of the FIFO of the memory 72. This can be realized by inputting the line effective reading width signal GATE.

As shown in the timing chart of FIG. 9, the input data of the signal C is input to the FIF○ memory 71 in synchronization with the line effective reading width signal LGATE, and the data of the previous line is output from the output terminal of the memory 71. , this 212in.
The frequency divider 7 sends a signal to write s to the FIFO memory 72.
By controlling with the output of 3, the output from the memory 72 is 2F.
! Output at the ins step. Similarly, memory 7
The signal obtained at the output terminal of 2 is delayed by one pixel by F/F 74, and the delayed pixel and the current pixel are launched by F/F 75 using the output signal of 172 frequency divider 77. A 2×2 block shown in FIG.

Pixel X in this 2×2 block + X21 x3.
If all of the pixels X4 are mark signals, the AND circuit 76 performs processing to treat them as mark signals, and if even one of the pixels X□ to It is possible to reduce erroneous detections in which a portion of the area is detected as a mark area.

Further, instead of using 2×2 blocks, it is also possible to perform the determination using blocks only in the main scanning direction or blocks only in the sub-scanning direction, and it is also possible to make the determination by increasing the matrix size. This makes it possible to prevent erroneous detection of marks outside the matrix area, and also simplifies the hardware configuration, which will be described later.

The mark width detection section 80 in FIG. 1 detects whether the mark width is greater than or equal to a certain width.

This detection is performed based on the fact that the mark always has convergence of a certain width or more, and in this embodiment, an area of 12 pixels x 12 mines is targeted. That is, in the embodiment, if the mark signal d exists with a certain probability or more in an area of 12 pixels x 12 Qine, it is regarded as a marked area. Here, the reason why a certain probability is set is that even if there is a slightly large white or black noise that is not cut by the mark noise removal section 60 described above, it is considered to be a mark area. Furthermore, by making the width of this mark larger than the width of normal characters/line drawings, the width of this mark can be reduced even in parts such as thin characters/lines that are mark signal candidates at the same density level as the mark density. By increasing the size, it is not determined that it is a mark, and false detection can be prevented.

In FIG. 10, the memory 81 is a FIFO memory and receives the 2Qine step data signal d as an input signal.
Data delayed 6 times in the sub-scanning direction, that is, 12 Qin
The data of e are aligned on the same time axis, and the arithmetic circuit 82
An AND operation and an OR operation are performed to calculate a probability of 5/6 for the same pixel in 12Rines. In other words, if the 5th step at the same pixel of data of 6X:1ine steps is mark signal d, it is output as a mark signal.

At this time, there are 6 combinations of 5 steps, and the 5-person AND operation is performed 5 times, and the sum of the AND outputs is ORed to realize a probability of 5/6.

This 5/6 probability signal in the sub-scanning direction is transferred to the shift register 8.
3, 6 tarokks in the main scanning direction (l/2 frequency division clock)
The arithmetic circuit 84 performs an AND operation and an OR operation on the mark signals corresponding to the delayed 9 clocks in the same manner as in the sub-scanning, so that the probabilities are 576 in the main-scanning direction. Through such calculations, main scanning, sub-scanning,
For each 12JineX12 pixels, if a mark signal is input with a probability of 5x6 or more, a mark width signal e is output.

The size of the width in mark width detection is variable depending on the system so as to be set to a value suitable for the system, and the above probability can also be set variably depending on the system. Furthermore, by having multiple different probability detection criteria, the first mark width detection is made stricter, and -
Once a mark has been detected, it is possible to improve the detection rate by lowering the probability of detecting the next mark width.

In general, digital copying machines have variable magnification functions, so in the embodiment, it is necessary to detect marks without error even under variable magnification settings.

In this magnification change, the sub-scanning magnification changes between the original and
Setting of magnification from reduction to enlargement is performed by mechanically changing the relative position with the CCD, and main scanning magnification is electrically changed by thinning pixels during reduction and interpolating pixels when enlarging. Double processing is performed. Here, electrical main scanning magnification change and original and C
The method of changing the relative position = speed of a CD can be realized by using a known technique, and will not be specifically explained.

32(a) and 32(b) are block diagrams showing the arrangement of the main scanning magnification unit applied to the embodiment, FIG. 33 is a block diagram showing the configuration of the main part of the embodiment, and FIG. FIG. 3 is an explanatory diagram of mark detection operation.

Here, the problem is the relationship between the mark area detection section and variable magnification. In other words, the sub-scanning image is an image obtained by scaling the input image in the sub-scanning direction according to the scaling. However, as shown in FIG.
03, or as shown in FIG.
One possible method is to detect the marked area.

Here, the method shown in FIG. 20(a) is one of the features of the present invention.
As mentioned above, this is a method in which mark area detection is performed before main scanning magnification change. By performing mark area detection before main scanning magnification change, mark width detection, which will be described later, is performed only in the sub-scanning direction in accordance with the magnification. Therefore, by adopting a configuration that allows multiple width detections depending on the magnification, it is possible to detect mark widths with a relatively simple configuration and without erroneous detection.

This false detection means, for example, as shown in FIG.
), when marking a mark with sufficient thickness in the reduction mode, the mark width becomes narrower, so conventional mark width detection detects the mark width corresponding to the same size, making it impossible to detect and causing false detection. arise.

For this reason, conventionally, when marking a mark in the reduced mode, it was necessary to mark it thicker. Furthermore, in Fig. 35(b), if there is line information (for example, thin pencil information) that is not a mark but has a density similar to the mark density, the line width is narrow at the same magnification, so there are cases where it is not detected incorrectly. By enlarging the line width, the line width may become suitable for the above-mentioned mark width detection, and a bar inspection may be performed.

The present invention aims to improve the above-mentioned drawbacks, and in the case of FIG. 32(a), the
This shows a case where mark area detection is performed after main scanning magnification change, and in mark width detection within this mark area detection, the third
As shown in FIG. 3, the above drawbacks are improved by providing a mark width detection section that detects the widths of a plurality of mark widths according to the magnification.

The input signal d in FIG. 33 is a signal determined to correspond to the mark density as a result of density detection.
The 33rd method makes a mark determination based on the presence of a pixel with a mark density in a block of eX12 pixels with a probability of 576.
A mark width detection circuit 410 shown in the figure is provided. In addition, in the embodiment, in the case of reduction mode (magnification x O, 5), 61
The mark width detection circuit 409 shown in FIG. 33 and the enlargement mode (
The mark width detection section is also equipped with a mark width detection circuit 411 shown in FIG. 33, which makes a mark determination based on the presence of a pixel with a mark density with a predetermined probability in a block of 24ρ1ne x 24 pixels when the magnification is x2). .

In addition, for mark width detection during reduction and enlargement, the 10th
This can be achieved by inputting the output of the memory 81 shown in the figure to the arithmetic circuit 82 and setting the output of the sub-scanning width shift register 83 corresponding to the magnification to the main scanning width corresponding to the magnification. Here, in order to output the mark width corresponding to each magnification, a selector 412 shown in FIG. 33 is provided, and the mark width output signal corresponding to each magnification is selected by a control signal from a CPU (not shown). Furthermore, if mark area detection is performed before main scanning magnification change, which is one of the requirements of the present invention, the above-mentioned main scanning width becomes constant, and the shift register 83 shown in FIG. 10 becomes fixed.

In particular, when the magnification is independent, that is, the main scanning magnification and the sub-scanning magnification are different, the mark width detection in the mark area detection unit 406 in the method shown in FIG. It is necessary to provide a mark width detection section corresponding to the magnification. However, in the case of the method shown in FIG. 32(a), only a mark width detection section corresponding to the magnification in the sub-scanning direction is required, resulting in a simpler circuit configuration.

In FIG. 1, reference numeral 90 denotes a first mark extension section, and this first mark extension section 90 is used because the signal obtained by the above-mentioned mark width detection section 80 is generally narrower than the actual mark area. It has a function to extend the signal to the actual mark area. FIGS. 11(a) to 11(c) are explanatory diagrams of mark magnification change, and the actual mark area R0 shown in FIG. Since the mark area R2 generally shrinks as shown in FIG. 3(c), correction is required. The figure (b) shows the mark area R1 calculated based on the mark width detection signal R.
This is the case when .

If the pixel of interest is a mark width detection signal, and adjacent pixels within a certain range are consecutive mark noise removal signals or mark density detection signals, the continuous minor noise removal signal or mark density detection signal area and mark In contrast to the algorithm that uses the width detection signal area as the mark expansion area, if the mark width detection signal is simply expanded after detecting the mark density and mark width, it has the disadvantage that errors will occur in the mark area. are doing. That is, as shown in FIG. 11, if the mark width detection signal is simply expanded, it may become larger than the actual mark area or may be smaller than the actual mark area, resulting in an error. For example, if the mark area is enlarged from the actual mark area, if there is information such as text in the vicinity of the mark area, that information will also be considered as the mark area, and the information that should remain may be missing or the information that you want to erase may be deleted. This causes the problem of remaining. Furthermore, when the mark area becomes narrow, there is a problem that the mark itself appears in the image.

FIG. 12 is a block diagram showing the configuration of the mark extension block of the embodiment, and FIG. 13 is a timing chart showing the operation of the mark extension block of the embodiment.

In the embodiment, the above-mentioned algorithm is realized by a mark extension unit as shown in FIG. In FIG. 13, the shaded area is the actual mark area, and the grid area is the above-mentioned mark width detection signal. In the timing chart, e and c are mark width detection signals and mark noise removal signals, and in the embodiment, it is sufficient to extend the reduced mark width detection signal to the mark noise removal signal.

Furthermore, in FIG. 13, if the dotted area is within the mark density range but has a narrow width, for example information written in a thin pencil, then e and c in the timing chart will have waveforms as shown in the same figure.

Here, the shift register 91 and the ○R circuit 92 in FIG.
This allows the mark width detection signal to be sufficiently expanded.

The amount of expansion needs to be greater than the area narrowed by the mark width detection described above. As shown in FIG. 13A4, in the embodiment, the first mark is smaller than the extended mark width detection signal, and exceptionally, the second mark is larger than the extended mark width detection signal. I assumed.

The output signal of the inverter 101 to which the mark noise removal signal is input and the output signal of the OR circuit g92 are input to the NAND circuit 95, and the signal A5 at the rear end of the first mark is taken out. Furthermore, in order to generate the tip end signal of the first mark, the mark noise removal signal C and the signal obtained from the shift register 102 are input to the OR circuit 103, and the signal A6 is sent to the output terminal of the OR circuit 103 to mark the mark using the NAND circuit 104. Signals e and N
A signal A7 is obtained by AND processing.At the rising edge of this signal A7, the first mark signal and the mark width detection signal area are combined and outputted, and the first mark signal and the mark width detection signal area are combined and outputted. It is possible to detect the leading edge of a certain amount of shift.

Furthermore, since the rear end side of the first mark signal must be shifted by the same amount as the shift amount obtained with signal A7, the shift register 99 matches the delay amount to obtain signal A8. Signal A7. By performing AND processing on A8 by the AND circuit 100, signals at the leading and trailing ends of the first mark area are synthesized. This signal controls the buffer 93 to output the signal A4 during the period when the signal is H. Signal A4 is input to shift register 94, which is also controlled by signal A9 described above.

In other words, during the H period of signal A9, signal A4, which is an extension of the mark width detection signal described above, is always input, and this causes the second
The signal obtained by extending the mark width detection signal and the signal obtained by extending the first mark width detection signal are transferred to the shift register 99,
It is expanded by a shift amount of 102.

In other words, the entire second mark area receives the mark width detection signal +
(shift amount X2), which is the same as extending the mark forward and backward. Therefore, as described above, the mark width detection signal can be extended to the actual mark area by the shift amount obtained from the actual mark signal, thereby solving the problems caused by simple extension. Furthermore, on the sub-scanning side, by replacing the shift register with a memory, it can be implemented using the same concept as mark extension in the main-scanning direction, but the explanation thereof will be omitted.

In FIG. 1, 110 is a mark connecting part, and in the second example, when a mark is painted on characters or line drawings, the first mark extension part 90
Since trace cuts may occur during the processing up to, the mark connection section 110 connects the trace cuts.

Fig. 14 is an explanatory diagram of mark connection processing, and Fig. 15 (a) (
Fig. 16 is a circuit diagram showing the structure of the mark connecting part of the embodiment, Fig. 17 (a) (b) is an explanatory diagram of preventing mark trace breakage.
) is an operational characteristic diagram of the mark connecting portion of the embodiment.

As an ``algorithm'', ``if the pixel of interest is a mark extension, the adjacent pixel is not a mark extension, the adjacent pixel is black or the mark level, and furthermore, a certain width of black or marks are continuous and the mark extension reappears within a certain width, it is constant. Pixels within the width that are not mark extensions are mark extensions.''

Conventionally, when the periphery of the mark is white, the conventional method of preventing marks from being cut off is done by extending the mark to a range R2, which is wider than the actual mark range R1, as shown in FIG. 15(a). Therefore, even information adjacent to a mark may be determined to be a mark. Furthermore, if there is a black image around the mark, the mark M spreads along this black image as shown in FIG. 10B, resulting in poor area accuracy.

As shown in FIG. 14(a), when a mark M is placed on the lettering, if mark expansion is performed, a cutout K will occur, so in this embodiment, the cutout part will be are connected by mark connection N.

In this case, the above-mentioned algorithm is implemented in the embodiment by a mark connecting section having the configuration shown in FIG. 16.

Although only the main scanning direction is shown in Figs. 16 and 17,
Since the sub-scanning direction can be considered in exactly the same way, its explanation will be omitted. In terms of configuration, the sub-scanning direction is realized by replacing the shift register in the main-scanning direction with a memory (for example, a FIFO memory).

First, mark M and lines L1 to L as shown in FIG. 17(b)
The case where 6 (black mark cut) exists will be explained.

Here, a case is shown in which the mark M is divided by lines L1 to L6, and the line is interrupted between lines L1 and L2 to the mark extension position described above. This is the mark extension signal f
It is assumed that the following is input to the mark connection unit 110 of the embodiment. Further, as is clear from the above description, a black or mark level signal is necessary in the mark connecting section 110, and this signal has a waveform as shown in the timing chart of FIG. 17(a). Line L1 and line L2 separated by mark expansion of the waveform obtained using these two signals f and b
Connect the areas of Furthermore, the regions separated by line L3 and line L4 are connected. And leave line L5 as it is and line L
It is sufficient to create a waveform that leaves 6 as well.

That is, when the mark is extended to JiL5, the line L5 as information becomes a mark signal, and in the case of masking, etc., the line L5 is divided. For this reason, in the present invention, as shown in the above-mentioned "algorithm", if a certain width of black or marks are continuous and a mark extension reappears within a certain width, the area that is not a mark extension is treated as a mark extension, and if the mark extension does not reappear, a mark is marked. Areas are not contiguous. Therefore, it is possible to connect marks with high precision by performing a trace breakage prevention process using this algorithm when a mark trace breakage occurs.

To realize this, first, mark expansion signal f is input to F/F1.
AND of the output after latching at 11 and the inverted signal of signal f.
The signal B1 is obtained by ANDing the processed signal in the circuit 112 and the black or mark level signal in the AND circuit 113. This signal B1 becomes a tip position signal where the mark extension is divided by the black mark break. Next, when the black or mark level signal is input, an area signal B2 of a subline of the divided area of the mark is obtained by OR processing of the mark extension signal f in the OR circuit 121.

This signal B2 is latched by the F/F 122 and ANDed with the mark extension signal f by the AND circuit 123, resulting in a rear end signal B3 of the divided signal of the mark extension area (only when there is a mark extension signal at the rear end). is output. Also, between the region signal B2 of the mark division area child line obtained by the above-mentioned OR circuit 121, the line L6 is excluded from the divided region of the mark extension signal by the above-mentioned mark extension trailing edge signal B1. (One of the features of the present invention) Furthermore, from the above-mentioned signal B1, the shift register 124 and the OR circuit]2
5 to produce a leading end detection signal B5 having a constant width, and an AND circuit 126 is used to detect whether or not the above-mentioned trailing end signal B3 is present within this signal B5 (that is, within one constant width). If it is determined by this detection that the trailing edge signal B3 is within a certain width, it means that the area divided by mark expansion is within a certain width (one of the features of the present invention).

In the embodiment, based on this signal B6, the area is further expanded by the above-mentioned constant width using a shift register 127 and an OR circuit 128. At this point, the current image signal and the signal B4 are delayed by a certain width, so the above-mentioned signal B4 is delayed by the shift register 116, and in order to determine whether or not the above-mentioned signal B4 exists between the signals B7, the F/F 117 latches it. The output signal B6 of the AND circuit 126 is latched by the F/F 118. Then, the AN of this signal and the above-mentioned delay-matched output signal B9 of the shift register 116 is
The signal BIO is obtained by AND processing by the D circuit 119. At this point, the area of line L5 is deleted (one of the features of the present invention).

Furthermore, the original mark extension signal f and the separated area signal 9
By performing OR processing with the OR circuit 120, the mark concatenation signal B]2(g) is obtained. In this way, the divisions due to black mark cuts within a certain width within the mark area are connected while leaving the line information outside the mark area. Since the line information in contact with the mark area is left, highly accurate mark connection is performed. Although only the main scanning direction has been described above, the sub-scanning direction can also be considered in the same way. Furthermore, processing in diagonal directions can be performed using the same concept, and by performing processing in this diagonal direction, accuracy can be further improved.

In FIG. 1, 140 is a second mark extension section, 150 is a first mark area detection section, and 200 is a second mark area detection section, and these parts will be explained in detail.

FIGS. 36(a), 36(b), and 36(c) are explanatory diagrams of images after marks are connected according to the embodiment, and FIGS. 37 to 39 are explanatory diagrams of conventional mark area detection.

In the embodiment, when the mark M placed on the lettering as shown in FIG. 36(a) is subjected to mark connection processing as described above, the image becomes as shown in FIG. 36(b), and I!
A translation detection unit E is generated for the X image. For this reason, in the embodiment, the erroneous detection portion E is removed by performing the same process as the first mark expansion, thereby achieving highly accurate mark area detection.

As an ``algorithm'', if the pixel of interest is a mark width detection signal (mark concatenation signal) and adjacent pixels are consecutive mark noise removal signals or mark density detection signals within a certain range, then the continuous mark noise removal signal area or Mark density detection signal area and mark width detection signal (mark continuous signal)
Let be the mark extension area. '.

In conventional mark area detection, as shown in FIG. 37, the part that is hidden from view in the shadow of the marker M from any of the X, x, and y directions is assumed to be the marker area. The same applies to the case shown in FIG. 38, and the portion that cannot be seen due to the shadow of the marker M from any direction x1x2y is considered to be the marker area. Furthermore, as shown in Figure 38,
Mark area M1 of marker M could not be detected.

Therefore, in the embodiment, a first mark area detection section 150 and a second mark area detection section 200 are provided to detect mark areas with high accuracy.

FIG. 18 is a block diagram showing the configuration of the mark area detection section of the embodiment, FIG. 19 is a circuit diagram of the 17th-kunilia detection section of the embodiment, and FIG. 20 is a circuit diagram of the second mark area detection section of the embodiment. 21 to 26 are timing charts of the mark area detection operation in the embodiment, and FIG. 27 (a
) to (C) are explanatory diagrams of area detection in the embodiment.

The algorithm detects positional information on the outside and inside of the marker designated area, and uses the detected positional information to detect the outside area and inverted area of the first mark area. Position information on the outside and inside of a certain second mark designated area is detected, and the outside area and inside area of the second mark area are detected based on the detected position information.The outside area and the inside area of the second mark area are detected. The combined output of the area outside the first mark area is fed back to the detection at the outside and inside of the first mark area.

In the embodiment, the above algorithm is realized by a mark area detection section having the configuration shown in FIG. 18th
In the mark area detection section shown in the figure, first, the above-mentioned second mark expansion signal is input to the first mark area detection section.

Based on this second mark expansion signal, the first mark outer position detecting section 151 and the first mark inner position detecting section 160
The outside area and inside area of the first mark are detected by the first mark outside area detection unit 152 and the first mark inside area, respectively, using the signals obtained by the first outside and inside position detections. This is performed by the area detection section 161.

In order to extract the second mark signal located in the area inside the first mark, a signal obtained by delaying the first mark signal by the delay circuit 158 and the inside area detection signal of the first mark are connected to an A N D circuit. 159, the second mark signal is extracted, and based on this signal, the second mark outer position detecting section 154 and the second mark inner position detecting section 163 perform "iK detection on the outer and inner sides as well." Each signal causes the second mark outer area detection unit 155 and the second
The mark inner area detection unit 164 detects the outer area and inner area of the second mark, and the OR circuit 165 performs OR processing of the outer area signal of the first mark and the inner area signal of the second mark. An AND circuit 157 performs AND processing between the obtained masking signal and the above-mentioned first mark outer area detection signal. This AND circuit 15
The output signal No. 7 is fed back to the first mark outer position detecting section 151 and the first □ mark inner position detecting section 160 to detect the outer and inner positions of the first mark.

First, FIG. 21 shows a case where the mark area expands in the sub-scanning direction. The signal f19 on the third line obtained from the second mark extension section 140 has a waveform as shown in FIG. Memory (F I F○) 1 in Figure 19
The front line signal obtained from 75 is Da, and the rear end signal of the mark on the front line is Db. The F/F 172 is a set/reset F/F, which is set at the leading edge of the second line signal Da and reset at the signal Db to obtain the second line outer signal DC.

This signal and the signal Dn obtained by the second mark area detection become the first line outer mark edge detection signal, so the signal D
d becomes equivalent to the outer mark area signal of the first line through the AND circuit 173.

This signal Dd is ORed with the second mark extension signal of the current line signal of the third line in an OR circuit 174 to obtain a signal De. This signal De becomes the first outer mark area signal of the third line when the mark spreads. This signal D
e is input to the FIFO memory 175, and read data from the memories 168 and 180 is output by the previous line signal.

By the way, the write data of the memory ]68 is the above-mentioned signal D.
The trailing end position information of the mark f19 on the current line is stored using the signal e latched by the F/F 170. This rear end position is information obtained by latching the position in the main scanning direction generated by the counter 166 by the F/F 167 at the inverted edge of the mark f19. Therefore, the mark trailing edge position information of the previous line is output from the memory 168, and the signal that is compared by the counter value outputted from the counter 166 and the comparator 169 becomes the signal Db, which becomes the above-mentioned mark trailing edge signal.

Similarly, write data in the memory 180 is transferred to the inverter 17.
8 and is the signal De inverted by the counter 166.
The counter value outputted by is a signal that is output as mark tip position information. Therefore, as the read data of the memory 180, the tip position information of the mark on the previous line 2 is output.

At this time, since the position information is output at the rising edge of the signal De (previous line), the counter 166 (i) becomes larger than the value output from the memory 180 and the comparator 181
The output Df becomes H. Also, F/F177 is set/
Reset F/F, signal D a and AN-D circuit 176
Since the signals from both are the same, the signal Dg becomes L. This signal Dg becomes an inner mark signal of the first mark area, and the signal at this time corresponds to the inner mark signal of line 2. Furthermore, the AND circuit 209 in FIG.
AND processing is performed on the signal of the line and the inner signal of the first mark area of the second line to determine whether or not there is a second mark area within the first mark area.

The circuit configuration in Figure 20 is almost equivalent to the circuit configuration in Figure 19, and the circuit in Figure 20 detects the outer area and inner area of the second mark area within the first mark area, but the overlap Explanation will be omitted. Here, since there is no second mark area, the signals Di and Dj become signals. These signals Di and Dj become the IQineth signal. Also, OR circuit 2
12° 214 is used to obtain an area signal for marker editing, which will be described later. That is, in the area outside the marker, the output signal Dn of the OR circuit 214 is the F signal, and in the area inside the marker, the output signal Dm of the OR circuit 212 is the E signal. Signal D here.

Dj is the second mark area number, signal Dk is the first mark area inner signal, and signal De is the first mark area outer signal (1Qins). Therefore, the signal Dn corresponds to the area outside the mark, and the signal Dm corresponds to the area inside the mark.

In this way, according to the embodiment, by independently detecting the mark outer area and the mark inner area based on the mark position information, and by providing the second mark area detection section, the mark area can be detected without ridge detection pressure. , it is also possible to detect mark areas within mark areas.

Furthermore, as already explained in the embodiment, by feeding back the signal output from the 27th-kunilia detection to the first area detection, the mark area can be detected with high precision and without error even if there is a recess on the sub-scanning side. As will be described later, multiple circular marks can also be detected without error by means of feedback.

FIG. 22 is an explanatory diagram of the mark area detection operation in the embodiment when a recess exists at the rear end of the mark area in the sub-scanning direction, and the recessed portion of the mark area is shown in the range of lines 1 to 7. .

The signal f19 of the current line 3 indicates that the second mark exists within the first mark. Memory 17 in Figure 19
The signal Da output from 5 indicates the state of line 2,
At this time, the outside of the first mark area is as described above.
/F 172 At this point, the feedback signal becomes the marker outside signal of the previous line 1, and the signal Dd becomes the marker outside signal of the second line (
(because the mark width is narrower). Furthermore, the inner signal of the first mark area on the second line also becomes the signal Dg as described above. Here, the second mark area within the first mark area is detected to obtain a signal Dh, and based on this signal Dh, the outer area and inner area of the second mark area are detected by the second mark area detection section 200. However, since this detection output is for the first line, both the signals Di and Dj are low, and the output signals of the OR circuits 212 and 214 become signals indicating the outer area and the inner area of the first line.

Area detection in the case of line 4 will be explained with reference to FIG. Similar to the third line, the output signal Dc is an area signal just outside the first marker on the third line, and the signal Dg is
The first marker is the inner area. Also, the signal Dj is 2
The signal Dj is L, which is the second marker outside the line.
bawl. Here, the signal Dm is a signal only inside the first mark area, that is, a signal only inside the mark area in a concave state. Further, the outer area signal is outside the first mark area, and the area output is detected without error.

The fifth line will be explained with reference to FIG. Similarly to the above, the signal DC is the outer signal of the first marker on the 4th line, the signal Dg is the inner signal of the first marker on the 4th line, and the signal D1
is a signal outside the first marker on the third line, signal Dj is a signal inside the first marker on the third line, and the signal DJ becomes L. Further, the signal Dm is a marker inner area signal of the third line, and the signal Dn corresponds to the marker outer area of the third line, and is the same as the signal of the third line outside the first mark area.

The operation on the 6th line will be explained with reference to FIG. As described above, the signal DC is the outer signal of the first marker on the 5th line, and the signal Dg is the inner signal of the first marker on the 5th line. Looking at the second mark area detection unit 200, the signal Dj becomes the second marker-outside area signal on the 4th line, and the signal Dj becomes the second marker-inside area signal on the 4th line. is output.

This signal Dj causes the signal Dn to be output as a signal outside the fourth line mark, and even if a concave mark area exists in the sub-scanning direction, the mark area can be detected without error. Of course, the signal Dm is a signal inside the mark on the fourth line, as described above. Further, by feeding back the signal Dn to the AND circuit 173 of the first mark area detection section 150, the signals Dd and De have the waveform shown in FIG. 25, and the data written to the memory 168 at this time is different from that described above. That is, in the above description, the position information on the outside of the rear end of the first mark area, ie, the position information at 340 in FIG. 25, is supposed to be written, but here, two position information, 234 and 340, are written. In other words, this is equivalent to the existence of two first mark areas.

Data written to memory 180 in the same manner.

Up to the above, position information of 285 on the 6th line inside the rear end of the first mark area should be written, but here, 185
Two pieces of position information, 1 and 285, will be written. Therefore, the signal outside the mark on the 6th line in FIG. 26 becomes Dc, which means that there are two areas outside the first mark. Furthermore, since there is no inner area corresponding to the two outer areas of the first mark on the sixth line, the signal Dg, that is, the inner area signal of the first mark on the sixth line becomes L.

That is, from this point on, only the first mark area is detected, and no mark exists within the first mark area. Therefore, as described above, areas with recesses in the sub-scanning direction can be detected correctly, and mark areas for multiplexing can also be detected correctly. This state is shown in FIG.

That is, in the embodiment, as described above, the outside and inside of the mark are detected at the same time, so the outside or inside of the mark can be arbitrarily selected depending on editing such as trimming masking. . Therefore, marks do not appear on the image unlike in the past, and the notch can be varied, reducing blurring of character lines and the like.

Next, editing of the mark area when the second mark area exists within the first mark area in the embodiment will be described.

For example, if you want to output an image of the first mark area and the second mark area (trimming), if you use the signal F from outside the first mark area to inside the second mark area, the mark itself will also be included in the image. In this case, the signal E from inside the first mark area to outside the second mark area is used. Furthermore, if you want to erase the images in the first mark area and the second mark area and output the other areas as images (masking), use the signal E from inside the first mark area to outside the second mark area. , the mark itself may also appear in the image, and in this case, the signal F from outside the first mark area to inside the second mark area is used. In this way, when using image @ editing such as trimming and masking, by using the above E and F signals separately, the mark itself is not output to the image, and therefore the density threshold for image binarization can be freely adjusted. The level can now be varied, so even if the input image information is light, such as text, it can be output darkly.

As described above, according to the embodiment, it is possible to detect a halftone and a portion surrounded by halftones, and the shape thereof is not limited to a rectangle but can be various. Further, the number of portions surrounded by halftones in one document is not limited. Furthermore, since the detection is performed in parallel with the document reading operation, there is no need to perform preliminary area detection by, for example, prescanning.

That is, for example, it is possible to extract a designated area and simultaneously copy the image of that area. Also,
In this embodiment, a mark made by a color felt tip pen is targeted, but as long as the mark is in a specific density range, other marks are irrelevant, and furthermore, a special sensor 5 light source is not required for detection.

FIG. 28 shows a detailed block diagram of the binarization and editing circuit. In addition, FIG. 31 shows that the editing data from the CPU is
The relationship between output data d corresponding to M3 is shown.

In FIG. 28, 395 and 396 are comparators;
97,398,306 is selector 399°300.30
3 is Invar 1 301,302゜304.305 is A
The ND gate 307 is a dither ROM.

First, a method of binarizing input data g will be explained.

In the case of character output, a comparator 95 compares the binarization level H from the CPU with the input data g, and outputs a binarization level r. Furthermore, by the dither method, the dither ROM 307 and the input data are compared in a comparator 396 as pseudo halftone output, and the dither data (halftone data) J
output, and if the operation board is in character mode, C
The data K from the PU becomes O, and the selector 397 outputs 1 as L.

In the case of halftone (photo) mode, the data from the CPU becomes 1, and the selector 397 outputs J to L. At this time, CPU data M1 to corresponding to the selector 306
M3 becomes O, and a signal corresponding to the input A of the selector 306 is output.

In addition, in marker editing mode, the marker corresponds to halftone density, so the input document is basically a character document with a high white/black ratio, that is, the background is whiter than the lower limit level of the marker. , it is assumed that the character data is blacker than the marker upper limit level.

As explained above, since the text M manuscript is targeted, K becomes 0 when editing the marker. When a signal comes in, the following processing can be performed.

FIGS. 29 and 30 are explanatory diagrams of masking and trimming processing in the embodiment.

(1) Masking 2 In other words, when erasing information in the mark area, an AND gate 301 performs the logical product of the signal obtained by inverting the mark area signal E by the inverter 300 and the binary image signal R. information is erased and input to the B input of the selector 306, and the old;1, M2 . By setting M3; O, masking data is output to the d output.

This output is shown in FIG. 30(a).

(2) Trimming: In other words, when extracting only the information within the marked area, the AND gate 302 performs the logical product of the marked area OF and the binary image signal, extracts only the information within the marked area, and selects the selector 306 M2:1. Ml,
By setting M3;O, masking data is output to the d output. This output is shown in FIG. 30(b).

(3) Black and white inversion inside the marker Image data outside the marker 2 In other words, only the information inside the marker of the image data is inverted in black and white, and the image data outside the marker is output as is. Image data and inverted data are selected by area signal E, and when a mark area signal is generated, inverted data is selected and output. Further, the CPU commands M1 to M3 are M1, M2: 1. M3:
OT: Yes.

This output is shown in FIG. 30(c).

(4) Outside marker black and white inverted image data inside marker 2 This is the signal obtained by inverting black and white outside marker image data (inside marker) in (3), which is inverted by the inverter 303, and the CPU commands M1 to M3 are Ml, M2:O,
M3: 1. This way of coming out is shown in FIG. 30(d).

(5) Black and white inversion within trimming marker: This is done by converting the image only in the marked area to
The ND gate 305 outputs the AND signal of the mark signal F and the inverted signal of the image data.
The commands M2 and M3 of PL- are.

Ml, M3: 1. M2: 0. The output is shown in FIG. 30(e).

(6) Black and white inversion outside the masking marker: This is the same way as the masking process in (1) for the image outside the marked area.
The D gate 304 outputs the mark signal E by the inverter 300 and the inverted image data signal, and the CPU commands M1 to N3 are Ml: O,
M2. M3: 1.

This output is shown in FIG. 30(f).

Further, in the mark editing of the embodiment, as shown in FIG. 28, a binarization means is used to perform mark area editing corresponding to a binary image. On the other hand, among digital devices, printers capable of multi-value output have recently been developed.

The mark area detection of the embodiment is not limited to the binarization described above, but can also be handled in a mode capable of multi-value output. In other words, the process up to area detection is performed as described above, and for example, 3
In the case of value output, add one more stage of comparator 395 in Fig. 28, and output the added comparator output from L'.
Then, the output from the selector 397 becomes two systems, L and L', in the character mode (mark mode), and by providing another circuit for the editing block shown in FIG. 28, it is possible to execute the mark editing mode with three-value output. is possible. In this case, the multi-level output can also have features such as being able to vary the threshold level corresponding to the output level, equivalent to the binary output.

The above-described embodiment configured as described above has the following effects.

(A) In mark area detection, the detection of the first mark area is performed using the threat signal together with the second mark area pressure detection signal within the first mark area. Even if the mark area is in a concave state, the mark area can be detected correctly. Therefore, there is no possibility that the character information in the concave part is not erased in the marker erase mode and the character information in the fourth part remains in the marker erase mode.

(2) Furthermore, even if there is a mark inside the recess,
Both the mark area of the recess and the mark area inside the recess can be detected correctly.

(3) Even if there are multiple circular marks as shown in Figure 34 (a), each mark can be detected, so when erasing within the marker, the inner line information can be extracted (Figure 34 (b) L marker In the case of outer erasure, it is also possible to extract the outer line information (see FIG. 34 (C), which enables complex mark area editing.

(B) Since the area inside the first mark area is detected, the second mark area within the first mark area can be detected. Therefore, when editing the mark area, the above (A
) is possible.

[Effects of the Invention] As explained above, according to the present invention, (1) even when the mark is concave on the sub-scanning side, the mark area can be detected correctly. Therefore, the character information in the recess is not erased in the inside-marker erase mode, and the character information in the recess does not remain in the outside-marker erase mode.

(2) Furthermore, even if there is another mark inside the recess, both the mark area of the recess and the mark area inside the recess can be detected correctly.

(3) Even if there are multiple circle marks, each mark can be detected, so it is possible to extract the inner line information when erasing inside the marker, and extracting the outer line information when erasing outside the marker. Mark area editing becomes possible.

[Brief explanation of the drawing]

1 to 36 are for explaining the present invention in detail. FIG. 1 is a block diagram showing the configuration of the main parts, and FIG. 2 is a block diagram showing the configuration of the main part, and FIG. FIG. 3 is a block diagram showing an overview of the overall configuration of the image processing device, and FIG. 4 is a characteristic diagram of the image processing device. FIG. 5 is a circuit diagram of the mark level detection section, FIG. 6 is an explanatory diagram of noise superimposition on marks, FIG. 7 is a circuit diagram of the mark noise removal section, and FIG. 8 is a circuit diagram of the blocking circuit section. 9th
The figure is a timing chart showing the blocking operation.
Figure 11 is a block diagram showing the configuration of the mark width detection section.
Figures (a) to (c) are explanatory diagrams of mark scaling, Figure 12 is a block diagram showing the configuration of the mark extension unit, Figure 13 is a timing chart showing the operation of the mark extension unit, and Figure 14 (a).
) to (c) are explanatory diagrams of mark connection processing, and Fig. 15 (a)
, (b) is an explanatory diagram of preventing mark trace breakage, Fig. 16 is a circuit diagram showing the configuration of the mark connecting part, Fig. 17 is a timing chart showing the operation of the mark connecting part, and Fig. 18 is the mark area pressure detection part. 19 is a circuit diagram of the first mark area detection section, FIG. 20 is a circuit diagram of the second mark area detection section, and FIGS. 21 to 26 are timing charts of mark area detection operation. , Figure 27(a)
~(c) is an explanatory diagram of area detection in the embodiment, and FIG.
A block diagram of the value conversion and editing circuit, FIGS. 29 and 30 are explanatory diagrams of masking and trimming processing, FIG. 31 is an explanatory diagram of output data corresponding to editing data from the CPU, and FIG. 32 (a) ( b) is a block diagram showing the arrangement of the main scanning magnification unit, Fig. 33 is a block diagram showing the configuration of the main parts, and Figs. 34 (a), (b), and (c) are markers erased by marks in multiplexing. and explanatory diagram of outside marker erasure processing, 3rd
5(a) and 5(b) are explanatory diagrams of the conventional mark detection operation shown for comparison, FIG. 36 is an explanatory diagram of the image after mark connection, and FIGS. 37 to 39 are diagrams of the conventional mark area detection. It is an explanatory diagram. 50... mark level detection section, 60... mark noise removal section, 70... blocking circuit section,
80... mark width detection section, 90... first mark extension section, 110... mark connection section, 140...
...Second mark extension section, 150...First mark area detection section, 200'...Second mark area detection section. Figure 2 Figure 3 Figure 5 Figure 7 Figure 11 fQ'2 Di H og=c L hl Di ' D, L Di ' Figure 23 Figure 24 Figure 25 Figure 26 Dg=CL hL 1 ' °“:) j5 j:KI Figure 27 Figure 29 Manuscript (C) (e) Figure 30 (b) (d) (f) Figure 34 (o) (b) (c) Figure 35 (b) ) Conjunction Figure 37 Figure 38 Figure 39

Claims (3)

[Claims] (1) a reading device that reads a document image and generates image information; a designation device that specifies a desired area of the document with a mark;
a first signal generating means for generating a designated mark reading signal; a second detecting means for detecting an area inside the mark; and a second detecting means for detecting an area inside the mark obtained by the second detecting means. a second signal generating means for detecting the mark and generating a signal; a third detecting means for detecting an area outside the mark in the main scanning direction using the signal obtained from the second signal generating means; 4th to detect the area inside
a detection means, a second synthesis means for synthesizing an inner mark signal obtained from the second detection means and an outer mark signal obtained from the third detection means, and the first signal generation means. a first detection means for detecting an area outside the mark in the main scanning direction using the mark reading signal obtained from the mark reading signal and a composite signal obtained by the second composition means; A mark area detection device comprising a first synthesis means for synthesizing a signal outside the mark and a signal inside the mark obtained by the fourth detection means. (2) means for reading a document image and generating image information; specifying means for specifying a desired area of the document by a mark; and a first signal generation device for generating a reading signal for the mark area specified by the specifying means. means, first detection means for detecting positional information of the outer rear edge of the mark by the first signal generating means, first storage means for storing the detected positional information, and reading of the first storage means. a control means for controlling writing, a second signal generation means for generating a signal based on the position information read by the first storage means, and detecting information on the outer tip position of the mark from the first signal generation means. a third signal generating means for generating an area signal outside the mark using the signals obtained from the second detecting means and the second signal generating means; and the first signal generating means. a third detecting means for detecting positional information of the inner rear end of the mark; and a second detecting means for storing the third detected positional information.
a storage means, a control means for controlling reading and writing of the second storage means, a fourth signal generation means for generating a signal based on the position information read from the second storage means, and a fourth signal generation means for generating a signal based on the position information read from the second storage means;
a fourth detecting means for detecting tip position information inside the mark using the signal generating means; and a fourth detecting means for generating an inner area signal of the mark using the signals obtained by the fourth detecting means and the fourth signal generating means. 5. A mark area detection device characterized in that it has a signal generating means according to No. 5. (3) Writing and reading of the first control means for controlling reading and writing of the first storage means and the second control means for controlling reading and writing of the second storage means are performed by the third signal generating means. The obtained outer area signal of the mark and the first
3. The mark area detection apparatus according to claim 2, wherein the mark area detection apparatus is controlled by a signal obtained by a combining means that combines the main scanning mark signal generating means.