JPH0420772U - - Google Patents
Info
- Publication number
- JPH0420772U JPH0420772U JP1990062484U JP6248490U JPH0420772U JP H0420772 U JPH0420772 U JP H0420772U JP 1990062484 U JP1990062484 U JP 1990062484U JP 6248490 U JP6248490 U JP 6248490U JP H0420772 U JPH0420772 U JP H0420772U
- Authority
- JP
- Japan
- Prior art keywords
- screen
- clamp
- sub
- signal
- parent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims 1
- 230000001172 regenerating effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Studio Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の一実施例を示す子画面用映像
信号のペデスタルクランプ回路、第２図は同第１
図を含む親子画面合成処理回路のブロツク図であ
る。
１はクランプパルスＢとクランプ電圧ＶＫ，Ｖ
Ｃとの子画面用映像信号のペデスタルクランプ回
路１ａ，１ｂ，１ｃからなるペデスタルクランプ
回路部、１０はクランプ用基準電圧回路、２１，
２４は輝度／色度信号分離回路、２２は親画面映
像信号用ペデスタルクランプ回路部、２３は親子
画面合成部、２５は子画面映像信号処置のピクチ
ヤ・イン・ピクチヤ回路である。
Fig. 1 shows a pedestal clamp circuit for a video signal for a small screen showing an embodiment of the present invention, and Fig. 2 shows a pedestal clamp circuit for a video signal for a small screen.
FIG. 2 is a block diagram of a parent-child screen composition processing circuit including a diagram. 1 is clamp pulse B and clamp voltage VK, V
A pedestal clamp circuit section consisting of pedestal clamp circuits 1a, 1b, and 1c for the video signal for the small screen with C, 10 is a reference voltage circuit for clamping, 21,
24 is a luminance/chromaticity signal separation circuit, 22 is a pedestal clamp circuit for a main screen video signal, 23 is a parent/child screen synthesis section, and 25 is a picture-in-picture circuit for processing a child screen video signal.
Claims (1)
輝度Ｙ信号と色差Ｒ−Ｙ、Ｂ−Ｙ信号とをそれぞ
れコンデンサを介して親子画面合成部の入力用増
幅器のベース回路に接続し、親画面映像信号用ク
ランプ基準電圧と共通のクランプ電圧によるクラ
ンプパルスを入力とする子画面用ペデスタルクラ
ンプ回路を同増幅器のそれぞれベース回路に付加
し、同増幅器よりそれぞれ直流分を再生した子画
面用輝度Ｙ信号と色差Ｒ−Ｙ、Ｂ−Ｙ信号とを出
力してなるテレビ受像機。 The luminance Y signal and the color difference R-Y, B-Y signals for the sub-screen of a receiver having a parent-child screen compositing function are respectively connected to the base circuit of the input amplifier of the parent-child screen compositing section through capacitors. A pedestal clamp circuit for the sub-screen which inputs the clamp pulse from the clamp reference voltage for the video signal and the common clamp voltage is added to each base circuit of the same amplifier, and the luminance Y signal for the sub-screen is generated by regenerating the DC component from the same amplifier. A television receiver that outputs color difference R-Y and B-Y signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990062484U JPH0420772U (en) | 1990-06-13 | 1990-06-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990062484U JPH0420772U (en) | 1990-06-13 | 1990-06-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0420772U true JPH0420772U (en) | 1992-02-21 |
Family
ID=31591676
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990062484U Pending JPH0420772U (en) | 1990-06-13 | 1990-06-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0420772U (en) |
-
1990
- 1990-06-13 JP JP1990062484U patent/JPH0420772U/ja active Pending
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