JPH04208534A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To detect the end point of polycrystalline silicon etching at a time when polycrystalline silicon is buried in an overhang section easily by forming a fourth insulating film while using a third insulating film as a mask before a second conductor film is buried. CONSTITUTION:Polycrystalline silicon 14 is applied on the whole surface, a cavity just under the polycrystalline silicon exposed to an overhang section is buried completely, and a thermal oxide film 11 on a sidewall and a sputtering silicon oxide film 13 are removed until they are exposed as the second polycrystalline silicon 14 is left as it is left to the overhang section 12. The sputtering silicon film 13 exposed is removed, the surface of an n-type epitaxial layer 3 is exposed, and a thermal oxide film 15 is formed on the surface of the epitaxial layer 3 and the sidewall sections of the polycrystalline silicon 14. Accordingly, the end point of polycrystalline silicon etching at a time when the polycrystalline silicon is buried in the overhang section 12 is detected easily.

Description

[Detailed description of the invention]

Purpose of invention] [00011

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high-performance, highly reliable bipolar transistor in which a base region and an emitter region are formed in a self-aligned manner with good controllability. [0002] [0002] A high-performance bipolar transistor device is
It is required in various application fields such as electronic computers, optical communications, and various analog circuits. Recently, several self-alignment techniques for base and emitter regions have been proposed, and the cutoff frequency of prototype bipolar transistors is about to reach 30 GHz. (For example, (i) IEEE Trans o
n Electron Device, vol, E
D-33°Apr, 1986. p, 526. (2)
JP-A-54-155778, (iii)
IEDM'86. 1986, p. 420,
(iv) Extended Abstracts
of the 19tn Conference
nce on 5 solid State De
vicesand Materials, Tokyo
, 1987pp331) [00031 FIGS. 6 to 9 are all cross-sectional views showing the manufacturing process of the conventional example in order of process. A wafer is used in which an n-type epitaxial layer 103 is formed on a p-type silicon substrate 101 via an n-type buried layer 1O2. An oxide film 104 is formed by selective oxidation in the element isolation region of this wafer, and a trench 105 and a p-type layer 106 are formed to serve as channel stoppers. After forming a thin first oxide film 107 on the surface of the element region of this wafer, a nitride film (S i3 N,+ film) serving as an oxidation-resistant mask is formed on the entire surface.
Deposit 108. Next, the first polycrystalline silicon film 10
9 is deposited, and poron is added to the first polycrystalline silicon film 109 by ion implantation. Then, a second CVD is applied to the entire surface.
An oxide film 130 is deposited, and the second CVD oxide film 130 and the first polycrystalline silicon film 109 on the emitter formation region are etched by photoetching to form an opening (FIG. 6).
). [0004] Thereafter, a thermal oxide film 110 is formed on the surface of the first polycrystalline silicon film 109 by heat treatment in an oxidizing atmosphere, and using this oxide film 110 as a mask, the nitride film 108 in the opening is heated with a phosphoric acid aqueous solution. Remove by etching. Then, the exposed thermal oxide film 107 is removed with an NH4F aqueous solution to expose the wafer surface. At this time, the nitride film 10 in the opening
By intentionally over-etching 8, an overhang portion 111 is formed and a portion of the first polycrystalline silicon film 109 is exposed (FIG. 7). [0005] Next, a second polycrystalline silicon film 112 is deposited on the entire surface to fill the cavity under the overhang part 111, and then the second polycrystalline silicon film is etched to form a CVD oxide film 130 and a thermal oxide film. 110 and the aperture surface is exposed (FIG. 8). [00061] Next, an oxide film 113 is formed by thermal oxidation on the exposed wafer surface and side surfaces of the polycrystalline silicon film. At this time, poron, which has been doped in the first polycrystalline silicon film 109, is diffused into the wafer through the second polycrystalline silicon film 112 of the overhang portion 111 to form a p-type external base layer 114. Form. After this,
A p-type internal base layer 115 is formed by implanting poron ions. Next, a CVD insulating film 116 and a third polycrystalline silicon film 117 are deposited, and these are etched by reactive ion etching, leaving them only on the side walls of the opening, and the third polycrystalline silicon film 117 is used as a mask to form the opening. The thermal oxide film on the wafer surface is removed. And a fourth polycrystalline silicon film 11 into which arsenic is ion-implanted at a high concentration.
8 is deposited, and arsenic is diffused by heat treatment to form an n-type emitter layer 119 (FIG. 9). The first and second polycrystalline silicon films 109 and 112 are used as base electrodes, and the fourth polycrystalline silicon film 118 is used as an emitter electrode. [0007]

According to the method for manufacturing a bipolar transistor as described above, the base and emitter are formed in a self-aligned manner, and the width of the emitter diffusion window is 0.4 mm.
A fine structure of 35 μm is possible. As a result, a bipolar transistor capable of high-speed operation is obtained. [0008] However, with this method, it is difficult to detect the end point of etching the second polycrystalline silicon film in FIG. 8, and over-etching easily occurs. Furthermore, even if over-etching does not occur, polycrystalline silicon cannot be etched uniformly due to its granular crystal structure, and the uneven etching shape also affects the etching of the single-crystal silicon die-cut surface. Unevenness occurs on the wafer surface. As a result, it becomes difficult to precisely control the fine diffusion region, resulting in a problem that a bipolar transistor that stably exhibits high-speed performance cannot be obtained. Furthermore, there is a problem in that the emitter-collector spacing varies due to unevenness on the wafer surface, and the breakdown voltage decreases with respect to the base width. SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that provides an improved bipolar transistor. [Configuration of the invention] [0009]

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes forming a first insulating film, an oxidation-resistant insulating film, on a semiconductor substrate having a first conductivity type collector layer separated by an element isolation region. a step of sequentially laminating and depositing a first conductor film, a step of adding impurity atoms of a second conductivity type to the first conductor film at a high concentration, and a step of depositing a second conductor film on the first conductor film. forming an opening by depositing an insulating film and removing the second insulating film and the first conductive film in the area where the emitter region is to be formed until the oxidation-resistant insulating film is exposed; a step of exposing the oxidation-resistant insulating film; a step of changing the exposed portion of the first conductor film to a third insulating film; and over-etching the exposed oxidation-resistant insulating film in the region where the base region is to be formed. a step of forming a cavity under the first conductor film; a step of etching away the exposed first insulating film until the semiconductor substrate is exposed; and a step of etching the exposed first insulating film until the semiconductor substrate is exposed; a step of anisotropically depositing a fourth insulating film thereon; and burying a second conductive film, which will become a part of the base electrode, in the cavity until the fourth insulating film is exposed. a step of etching the film; a step of etching and removing the fourth insulating film until the semiconductor substrate is exposed; and forming a thermal oxide film on the semiconductor substrate exposed in the opening and on the sidewalls of the second conductor film. At the same time, a step of diffusing impurity atoms of a second conductivity type added in advance to the first conductor film into the collector layer to form an external base layer of the second conductivity type; a step of adding impurity atoms of a second conductivity type to the semiconductor substrate to form an internal base layer of the second conductivity type; a step of exposing the semiconductor substrate in the opening where the internal base layer is formed; and a step of exposing the semiconductor substrate in the opening in which the internal base layer is formed. a step of depositing a third conductor film to become a part of the emitter electrode, and a step of diffusing impurity atoms into the semiconductor substrate through the third conductor film to form an emitter layer of the first conductivity type. The main feature is that it contains [00101

[Operation] The present invention provides a fourth insulating film using the third insulating film as a mask before embedding the second conductive film. [0011] This makes it easier to detect the end point when etching the second conductor film, and provides a flat semiconductor surface in the area where the emitter region is to be formed, regardless of the etching shape of the second conductor film. This eliminates variations in the shape of the first conductivity type emitter layer, which is formed by diffusing impurity atoms onto the semiconductor surface via the third conductor film, and provides a bipolar transistor that stably exhibits high-speed performance. The problem that the withstand voltage between the emitter and collector decreases also does not occur. [0012] Embodiments Examples of the present invention will be described below with reference to the drawings. 1 to 5 are cross-sectional views showing a method for manufacturing a bipolar transistor according to an embodiment of the present invention in the order of steps. [0013] For element isolation of a bipolar transistor, an n-type high concentration impurity layer 2 is formed on a p-type silicon substrate 1, and an n-type relatively low concentration layer (~I x 10
After forming an epitaxial layer 3 with a thickness of 16 cm by a vapor layer growth method, a trench region 4 for element isolation and an electrode isolation region for separating the base emitter region and the collector contact region are formed using trench technology and selective oxidation technology. An insulating oxide film 5 is formed.The n-type highly impurity layer 2 is connected to a collector contact (not shown), so the epitaxial layer 3 made of a low concentration epitaxial layer forms a part of the collector. A thermal oxide film 6 with a thickness of about 500 A is formed on the entire surface of the silicon substrate by thermal oxidation, and a silicon nitride (Si3N) film is further formed as an oxidation-resistant insulating film on the entire surface including the trench region and isolation insulating film region.
4 film) 7 was deposited at 1000A. Next, a polycrystalline silicon film 8 is grown to a thickness of about 4000 Å over the entire surface as a first conductor film. Next, poron ions are implanted into the polycrystalline silicon film 8 under the conditions of 50 keV and IXI 016 cm-3. Subsequently, a CVD silicon oxide film 9 of about 3000A is sequentially deposited as a second insulating film on the entire surface (
Figure 1). [00141] Next, the second oxide film 9 and first polycrystalline silicon 8 on the region that will later correspond to the emitter diffusion region are removed by photolithography and etching until the underlying silicon nitride film 7 is exposed. Then, an opening 10 having an opening width of 1 μm is formed. [0015] Then, 950°C wet oxidation was performed,
A thermal oxide film 11 having a thickness of about 2000 Å is formed on the side surface of polycrystalline silicon 8. Next, using this thermal oxide film as a mask, the silicon nitride film 7 in the opening is heated with phosphoric acid to form the underlying first oxide film 6.
Remove until exposed. This etching is done by intentionally over-etching even after the underlying oxide film is exposed.
The silicon nitride film 7 is side-etched by about 3000 Å to form a cavity 12 directly under the polycrystalline silicon. Thereafter, the exposed first thermal oxide film 6 is removed by etching with NH, +F solution, or the like. Next, using the thermal oxide film formed on the side wall as a mask, a silicon oxide film 13 of about 500 Å is deposited by sputtering on the surface of the n-type silicon 3 exposed in the opening 41 (FIG. 2). [0016] Thereafter, a polycrystalline silicon 14 of about 3000 A is deposited on the entire surface as a second conductor film, and the cavity directly under the polycrystalline silicon exposed in the overhang part is completely filled, and the second polycrystalline silicon 14 is deposited. Overhang part 1
The thermal oxide film 11 and the sputtered silicon oxide film 13 on the sidewalls are removed until they are exposed while leaving them on the sidewalls (FIG. 3). [0017] The exposed sputtered silicon film 13 is treated with N H
After removing the n-type epitaxial layer 3 by wet etching using a 4F solution and exposing the surface of the n-type epitaxial layer 3, a layer of 700 nm is etched on the surface of the epitaxial layer 3 and the sidewalls of the polycrystalline silicon 14.
A thermal oxide film 15 of approximately A is formed. At this time, poron, which has been added to the first conductor film in advance, is diffused into the underlying silicon substrate through the polycrystalline silicon in the overhang portion to form a p-type external base diffusion region 16. Next, boron is applied through the thermal oxide film 15 at 20keV, 2X1013C.
Ion implantation is performed under the conditions of 1.m'' to form a p-type internal base region 17 in the n-type epitaxial layer 3.
Polycrystalline silicon 19 is continuously deposited for approximately 2,000A and polycrystalline silicon 19 is deposited for approximately 2,000A, and the polycrystalline silicon 19 is removed by directional etching until the CVD silicon oxide film 18 is exposed to form a sidewall. Using this sidewall as a mask, CVD silicon is The oxide film 18 and the thermal oxide film 15 are removed by directional etching, the surface of the epitaxial layer 3 is exposed, and an emitter opening is formed (FIG. 4). The polycrystalline silicon film 20, which is the third conductor film, is deposited on the entire surface to a thickness of about 250 OA by photolithography and ion-implanted with arsenic under the conditions of 50 keV and 1Xl016 cm-2, and the third conductor film 20 is deposited by photolithography and photolithography to cover the opening. Formed by etching method. Furthermore, a desired heat treatment is performed, and arsenic added to the polycrystalline silicon serving as the third conductor film is diffused into the silicon substrate to form the n-type emitter region 21, and at the same time, form the final external base region and internal base region. (Figure 5). [0020] Thereafter, a base contact is formed on the first polycrystalline silicon 8 using photolithography and etching, and an aluminum electrode wiring is further formed to form a bipolar transistor. (not shown) [00211
In the above embodiment, CVD technology was used to fill the polycrystalline silicon film into the overhang part 12.
After forming the polycrystalline silicon film 3, by depositing a polycrystalline silicon film only on the overhang portion where the silicon oxide film is not attached using selective CVD technology, it is also possible to fill the overhang portion without etching. [0022] Furthermore, if it is desired to reduce the link area between the internal base and the external base for the purpose of reducing base resistance, this can be achieved by the following process. That is, by using directional etching in etching the second conductor film in FIG. 3, the gap between the second conductor film embedded in the overhang portion and the third conductor film forming the emitter electrode is The thermal oxide film can be formed vertically, and even if the side walls of the groove 10 formed by the CVD silicon oxide film 18 and the polycrystalline silicon film 19 are made thin, sufficient insulation can be obtained. This allows the base resistance to be lowered and a high-speed bipolar transistor to be obtained. This invention can be modified and implemented in various ways without departing from the spirit thereof. [0023]

As described above, according to the present invention, it becomes easy to detect the end point of polycrystalline silicon etching when embedding polycrystalline silicon in an overhang portion, and it also eliminates uneven etching rates of polycrystalline silicon. The unevenness of the etched surface no longer affects the epitaxial silicon layer. Therefore, a bipolar transistor with excellent characteristics such as junction breakdown voltage and cut-off frequency, and with little variation in these characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process.

FIG. 2 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process.

FIG. 3 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process.

FIG. 4 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process.

FIG. 5 is a cross-sectional view showing the manufacturing process of a bipolar transistor according to an embodiment of the present invention in order of process.

FIG. 6 is a cross-sectional view showing the manufacturing process of a conventional bipolar transistor in order of process.

FIG. 7 is a cross-sectional view showing the manufacturing process of a conventional bipolar transistor in order of process.

FIG. 8 is a cross-sectional view showing the manufacturing process of a conventional bipolar transistor in order of process.

FIG. 9 is a cross-sectional view showing the manufacturing process of a conventional bipolar transistor in order of process.

[Explanation of symbols]

Claims (1)

[Claims] 1. A first insulating film on a semiconductor substrate having a first conductivity type collector layer separated by an element isolation region;
A step of sequentially laminating and depositing an oxidation-resistant insulating film and a first conductor film, a step of adding second conductivity type impurity atoms to the first conductor film at a high concentration, and a step of adding the first conductor film to the first conductor film. forming an opening by depositing a second insulating film thereon and removing the second insulating film and the first conductive film in the area where the emitter region is to be formed until the oxidation-resistant insulating film is exposed; a step of exposing the oxidation-resistant insulating film in the opening, a step of changing the exposed portion of the first conductor film to a third insulating film, and a step of exposing the exposed oxidation-resistant insulating film to the area where the base region is to be formed. A step of etching to form a cavity under the first conductor film, a step of etching and removing the exposed first insulating film until the semiconductor substrate is exposed, and forming an emitter region using the third insulating film as a mask. A step of anisotropically depositing a fourth insulating film on the semiconductor in a planned area, and burying a second conductive film that will become a part of the base electrode in the cavity until the fourth insulating film is exposed. a step of etching a second conductive film; a step of etching away the fourth insulating film until the semiconductor substrate is exposed;
A thermal oxide film is formed on the semiconductor substrate exposed in the opening and on the side wall of the second conductor film, and at the same time, second conductivity type impurity atoms added in advance to the first conductor film are diffused into the collector layer. forming an external base layer of a second conductivity type; adding impurity atoms of a second conductivity type to an exposed portion of the opening of the semiconductor substrate to form an internal base layer of a second conductivity type; a step of exposing the semiconductor substrate in the opening in which the internal base layer is formed; a step of depositing a third conductor film to become a part of the emitter electrode on the entire surface of the semiconductor substrate; A method for manufacturing a semiconductor device, comprising the step of diffusing impurity atoms into a semiconductor substrate to form an emitter layer of a first conductivity type.