JPH04209057A - Chain command operation check system in data transfer request processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figures 4 to 8) Means for solving the problem to be solved by the invention (Figure 1) Effect (Figure 1) Figure 1) Embodiment (Figures 2 and 3) Effects of the invention [Summary] Regarding a method for checking chain command operation in a data transfer request processing device, the operation of a data channel device and a data input/output device is checked based on communication data. A central control unit, a storage device with a transmission data buffer,
A data channel device that starts chain command operations in response to a startup command from a central controller.

It is equipped with a data input/output device that operates with chain commands, has an operation check area in the storage device that checks the operation of chain commands, and includes a reset command to reset the operation check area in the chain command, and also By setting the operation check area for each required time using a signal, if the operation check area is reset before the predetermined time elapses, it is considered to be normal operation, even after the predetermined time elapses.

If the operation check area is not reset, it is configured so that a failure occurs.

[Industrial Application Field] The present invention relates to a method for checking chain command operation in a data transfer request processing device.

In other words, in device control of a device that processes randomly occurring data transfer requests, such as a common line signaling device, the central processing unit (CC) and data channel device (D
The chain command method is adopted from the viewpoint of transfer capability of CH.

In this chain command method, the data input/output device [1 (I
Since the central processing unit (CC) does not know whether the central processing unit (O device) is operating normally, it is necessary to check its operation.

[Prior Art] Now, FIG. 4 is a block diagram showing the input/output operation of a conventional data channel device (DCH). In FIG. 4, 102 is a memory device (MM), and this memory device 10
2 is data 102a, 102b, 102 for starting the data channel device (DCH) 103;
The control unit 102A that stores c and the data channel device (
Data transfer area 10 equipped with a transmission data buffer for DCH) 103 to perform transfer operations (see 103B)
2B.

101 is a central processing unit (CC), and this central processing unit 1
01, a start signal is output to the data channel device (DCH) 103 by a start IO command (SIO command) (see 101A). Furthermore, this SI○
The content of the command is the channel number (CHA) and IO number (■
This command causes the data channel device 103 to read the command address word (CAW) 102 from the specified address of the memory device (MM) 102.
a is loaded.

Further, in the central control device 101, the data input/output device 10
Inspection of the condition code (CDC) issued from the data channel device @103 in response to the activation result of step 4 (101
(see B).

Further, the central control unit 101 is notified by the data channel device 103 that the data transfer has ended (see 103C) by means of an interrupt (see 101C). Note that at this time, the data channel device 103
The interrupt information possessed by the bus command is set in the bus command.

103 is a data channel device, and this data channel device 103 receives data CAW from the storage device 102 [This CAW is fixedly allocated to the storage device 102 in correspondence with the data channel device 103, and CCw (
Indicates the storage location of channel command word) 102b]
is received in response to an activation signal from the central control unit 101 and loaded into the register of the data channel device 103, thereby performing the activation operation (see 103A).

Then, the CCW 102b is read from the storage device 102, and read and write operations are performed autonomously according to the CCWIO 2b (see transfer operation 103B).

104 is a data input/output device, and this data input/output device i
! 104 is a startup operation 10 of the data channel device 103.
3A (see 104A), it performs input/output operations to the common line (see 104B).

And this data input/output bag! (At 104, the transfer operation is ended in response to the end signal from the data channel device 103 (see 104C), and the input/output operation is ended (see 104D).

Incidentally, the configuration and storage state of each data 102a, 102b, 102c for controlling the data channel device 103 are shown in FIGS. 5(a) to 6(d) and FIG. 6, respectively.

Here, FIG. 5(a) shows the configuration of the CAW (command address word) 102a, and this CAW I O2
a is stored in the system area of the storage device 102,
The storage address CMA of CCW102b is stored in bits 0 to 23.
24 to 29 bits are all O, 30.31 bit is K
EY is written respectively.

FIG. 5(b) shows CCW (channel command word) 102
This CCW 102b is composed of two words, with WC (data transfer amount) in bits 0 to 11 of ccwo, and FLAG (flag: this includes chain command display CC) in bits 19 to 23 of ccwo. But 24~
CMC (command code: designation of read and write operations) is set at 31 pin i-, and CMC is set at 0 to 23 pins 1 to I) of CCWl.
A (data transfer destination address) is written respectively.

FIGS. 5(C) and 5(d) show the configuration of the CSW 102c, and this C8W 102
c is information indicating how far the data transfer sequence has progressed, and is stored in the system area, and if a failure occurs in the data input/output bag W104 or data channel device 103, or if the data transfer is completed, The central control device 101 is notified.

Furthermore, the CSW 102c is composed of two types, C3WA and C3WB, and FIG. 5(c) shows the csWA. status of device 103)
However, DST [input/output status in device status: state decoration MOD (this MOD
has the function of skipping the ccw of the next address on the storage device 102 when it is 1)], and wc (data transfer amount) is written in the 20th to 31st bits, respectively.

Figure 5(d) shows C3WB, one word 4
．． 1:, C5T, DST, and WC are written in the same way as C3WA, and also written in the other word.

10A (attendance address) is 30 in bits 20-27.
KEY is written to 31 bits respectively.

FIG. 6 shows the system area of the data channel device (DCH) 103. For example, from address 14 (H) to data channel number 0 (DCHO) are CAW, C5WA, C
Written as a set of 3WBO, C3WBI, then address 1
8 (H) to data channel number 1 (r+cH1) are the same set, and data channels number 2 to 6 (DC
02 to 6) are written in a similar set, then address 3ON(
) to data channel number 7 (DCH7) are written in a similar set.

With the configuration described above, the data channel device 103 performs the following activation, transfer, termination, and reporting operations.

(1) Start-up operation 103A ■Central processing unit 101 issues input/output command (SIO command) 10
When 1A is executed, an activation signal is sent to the data channel device 11103.

■ Upon receiving the activation signal, the data channel device 103 stores CHW (channel word:
■Assigned to O device and shows the transfer status of each IO)
is read and the specified data input/output device 104 is free/
Check for blockages.

As a result, if it is empty, the control unit 102A of the storage device 102 transfers the CAW 102a to read the CCWIO2b.
, and load it into the register of data channel device 103. As a result, when the data channel device and data input/output device are specified, the C
Data transfer is performed autonomously according to the CW 102b.

(2) Read the CAW 102a and CCW 102b and start the specified data input/output device 104.

■The activation results of the data input/output device 104 are sent to the central controller 1.
01 Return with condition code CDC. If it is good, the roOJ will be returned.

(2) Transfer operation 103B When the central processing unit 101 receives the condition code CDC from the data channel device 103, the central processing unit 101 receives the data transfer area 1 in the data input/output device 104 and the storage device 102.
Data channel device 1 controls data transfer between 02B and 02B.
03 and executes other programs until it receives the data transfer completion report 103C from the data channel device 103.

(3) Termination/Reporting Operation 103C ■ When the transfer of data specified by CCW (channel command word) is completed, the data channel device 103 issues a termination instruction to the input/output device 104.

(2) When the input/output bag W104 performs an input/output operation, it sends a device completion report to the data channel device 103.

(2) When the data channel device 5103 receives the device termination report, it rewrites C3WI 02c (channel status language) indicating the channel operating status. In addition, CS
Similar to CA W 102 a, addresses are fixedly assigned to W 102 c.

(2) Notify the central processing unit 1101 that the data transfer has been completed using an interrupt. At this time.

Interrupt information (IS number) possessed by each data channel device 103 is set in the bus command. Also.

Interrupt disabled FF (M
Similar IS) is also set.

Incidentally, a chain command method is provided as a means for causing the data channel device 1.about.3 to operate as described above.

Next, an outline of this chain command method will be explained using FIG. 7-8.

First, the data channel device 103 is activated by an SIO command from the central processing unit 101, and the CCW at that time is as shown in FIG. That is, in order from the top of the address, write pattern (WPT) command, TIC command, write (WRT) command, read pattern (RPT)
) command and TIC command. Here, C
The actual CW exists in the storage device @102, and the data channel device 103 sequentially retrieves and executes the CCw in the state shown in FIG. 8 while passing through the CAW. Further, in the case of a chain command, the CC (chain command display) of CCw is -“1”.

Further, the operation of the data channel device 103 is as follows.

(1) Take out the CCW from the storage device 102 and perform startup, transfer, and termination operations.

(2) In the final operation, if the CC of the CCW (displayed to chain command 1) is "1", it is determined to be a chain command, the CCW at the address of the link on the storage device 102 is retrieved, and the above (1) is performed. Do this.

(3) In the final operation of (2) above, CC=1 and C3W
B When the DST MOD=1 in [see Figure 5(d)], there is a function to skip the CCW of the next address on the storage device 102, so use this function to execute the EF command with the WPT command.
C (This EFC is set in the transmission data buffer 102d, and when there is a data transfer request, the central processing unit 1
is set to 1 by E F
When C=1, MOD=1 is set and the WRT command is executed.

The manner in which the data channel device 103 autonomously executes the command indicated by the CCW is shown in the flow (S1) written in the data channel device 103 in FIG.
01 to 5105), and such a series of processing is called chain command processing (see 103S).

Therefore, after starting the data channel device 103 with an SIO command from the central processing unit 101, if there is no data to be transmitted in this data channel device 103,
When there is rule 1-2 transmission data in ■ in Figure 7,
Autonomous operation with the data input/output device 1104 is entered by the route (■) in the figure.

Note that when the central processing unit 101 receives a data transfer request, it sets the EFC of the transmission data buffer 102d to 1,
Since the sending data is set, if there is sending data,
The data is transferred by taking the route (■) in FIG.

[Problem to be Solved by the Invention] By the way, in the chain command method described above, the central processing unit 101 does not know whether the data input/output device 104 is operating normally (whether it is operating autonomously by the chain command). Since I don't know, I am using the following method to check its operation.

That is, after a data transfer request is issued and EFC of the transmission buffer 102d is set to 1, it is monitored whether EFC is reset to O within the required time and EFC is set to 1.
When C does not become 0, it is determined that it is not operating.

However, with this method, if there is no data to send,
Since EFC cannot be set to 1, it is impossible to confirm that it is reset to 0, and there is a problem in that an operation check cannot be performed.

This causes a problem in that failure detection in the data input/output device 104 is delayed and reliability of the entire transfer device cannot be ensured.

The present invention was devised in view of these problems, and is capable of quickly checking the operation of a data channel device and data input/output device even when there is no communication data.
The purpose of this invention is to provide a method for checking chain command operation in a data transfer request processing device.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In FIG. 1, reference numeral 1 denotes a central control unit (CC), and this central control unit 1 controls a memory device (MM) 2 and a data channel device (DCH) 3.

2 is a storage device, and this storage device 2 includes a transmission data buffer 2a and an operation check area 2b.

Here, the transmission data buffer 2a is a memory that temporarily stores transmission data, and the operation check area 2a is a memory area for checking the operation of the chain command 3S in the data channel device 3.

3 is a data channel device, and this data channel device 3
The chain command 3S is started by a start command from the central control device 1, and a reset command for resetting the operation check area 2b is included in the chain command 3S. Note that CCW (channel command word), which is the substance of the chain command 3S, is stored in the storage device 2.

4 is a data input/output device, and this data input/output device 4 is
Input/output operations are performed by chain command 3S of data channel device 3.

[Function] In the chain command operation check method in the data transfer request processing device of the present invention described above, the operation check area 2b is set by the main controller 1 at each required time, but if the data channel device 3 does not operate normally. If it is, the reset command will reset it within a predetermined time regardless of the presence or absence of transmitted data, and normal operation will be confirmed.

On the other hand, if it is not operating normally, the operation check area 2b is not reset and after a predetermined period of time it is detected that it is not operating normally, and it is assumed that a failure has occurred.

[Example code] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, and FIG. 3 is a diagram for explaining the main part configuration of this embodiment. In these FIGS. A central control unit (CC), 2 a memory device (MM), 2a a transmission data buffer, and 3 a data channel device! (DCH), 3S
4 is a chain command, and 4 is a data input/output device (10), which are respectively connected to the central controller 101 . Storage device 1o2. Transmission buffer 10
2d, data channel device t103. It is configured almost the same as the chain command 103S and the data input/output device 1104, and transfers data using the same operation.

Note that 5 is an exchange for exchanging data such as voice.

6 is a common line for control data to be transferred.

In addition, S] to S8 in the chain command 3S indicate processing steps, and steps S1 to S8 among these indicate the processing steps.
5 is the chain command I-103S mentioned above as a conventional example.
It performs almost the same operation as each of the STETSU7's 8101 to 5105.

By the way, the following items are newly provided in this embodiment.

First, an operation check area 2b is provided in the storage device 2. Here, this operation check area 2b is designed to store OPC (operation code) of 0 to 1 bits.

Next, a periodic program IS is provided in the central processing unit 1. Here, this periodic program 1S is repeatedly executed, for example, every second, and performs an operation such as setting OPC to 1 in the operation check area 2b of the storage device 2 in step S12.

In addition, in the chain command 3S, step S6 includes an operation code (
It has a function to clear (opc).

Step S7 has a function of clearing the operation code (OPC) in the route where there is no data to be transferred (the route after there is data in step S1).

In step S8, in the route when there is no data,
This means a jump process that returns the process to step S1.

With the dual configuration, the data channel device 3 is activated by the central control device 1 and performs almost the same operations as the conventional one.

In addition, a periodic program IS is activated in the central control unit 1 and repeated at required time intervals, for example every second.

That is, in step Sll in the same program IS, it is determined whether the operation code (OPC) of the operation check area 2b in the storage device 2 is 0, and if it is O, the operation code (OPC) is
c) is set to 1 (step 512), and the error count (ERRCNT) is cleared to 0 (
Step 513).

On the other hand, the chain command 3S is also repeated at the required period, but if this chain command 3S is operating normally, the operation code (opc) is reset and cleared to O in step S7 for routes where there is no transfer data. , for routes with transferred data, step S
6, the operation code (opc) is reset and cleared to O.

By the way, if the chain command 3S is not operating normally, step S6. Since S7 is not executed and the operation check area 2b of the storage device 2 is not reset,
At step Sll in the periodic program IS of the central control device 1, it is determined that OPC≠0, and step S14
is executed.

In step S14, it is determined whether ERRCNT is greater than a required number N.

Also, when step S14 is executed for the first time, E
Since RRCNT has been cleared to 0, ER
Since RCNT<N, step S16 is executed and 1 is added to ERRCNT.

That is, ERRCNT continues to increase by 1 each time step S16 is passed, and when it exceeds the required value N, it is assumed that a failure has occurred in the chain command 3S or the data input/output device 4, etc., and the failure is determined in step S15. Processing is executed.

In this way, the operation of the data channel device can be quickly checked even when there is no communication data, so the reliability of the entire transfer device is greatly improved.

In addition, as written in the memory table W2 of FIG.
command, RPT command, RPT command, TIC command F, RPT command.

This command is a TIC command, its substance is in the storage device 2, and when executed, the CCW is retrieved via the CAW. Therefore, the data channel device 3 of FIG.
The flow in the figure shows how the data channel device 3 autonomously executes the command indicated by CCW.

[Effects of the Invention] As detailed above, according to the chain command operation check method in the data transfer request processing device of the present invention,
Since the operation check area 13 in the storage device is constantly set by the central controller and reset by the chain command of the data channel device, even if there is no data to be transmitted by the data channel device, the operation of the chain command cannot be performed. This has the advantage that if a failure occurs in a chain command, it can be quickly detected and processed, and as a result, it can greatly contribute to improving the reliability of the entire transfer device.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a diagram showing the main part configuration of an embodiment of the present invention, and Fig. 4 is a conventional block diagram. 5(a) to 5(d) are schematic diagrams showing the control data structure of the data channel device, and FIG. 6 is a diagram showing the control data storage of the data channel device. The schematic diagrams illustrating the state and FIGS. 7 and 8 are diagrams each explaining the outline of the chain command method. In the figure, 1 is a central control unit, IS is a periodic program, 2 is a storage device, and 2a is a transmission data buffer. 2b is an operation check area, 3 is a data channel device, 3S is a chain command, 4 is a data input/output device, 5 is a switch, and 6 is a common line. 101 is a central control unit, 102 is a storage device, 102d is a transmission data buffer, 103 is a data channel device, 103S is a chain command, and 104 is a data input/output device.

Claims (1)

[Claims] An apparatus for processing data transfer requests, comprising: a central control unit (1); a storage device (2) having transmission data and a buffer (2a);
and a data channel device (3
) and the chain command (3) in the data channel device (3).
A data input/output device (4) that operates with the chain command (3S) is provided, and an operation check area (2b) is provided in the storage device (2) for checking the operation of the chain command (3S). ) by inserting a reset command to reset the operation check area (2b) and setting the operation check area (2b) at each required time using a signal from the central control device (1). If the operation check area (2b) is reset before, the operation is determined to be normal, and if the operation check area (2b) is not reset even after the predetermined time has elapsed, it is determined that a failure has occurred. A chain command operation check method in a data transfer request processing device.