JPH04209559A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH04209559A
JPH04209559A JP2400352A JP40035290A JPH04209559A JP H04209559 A JPH04209559 A JP H04209559A JP 2400352 A JP2400352 A JP 2400352A JP 40035290 A JP40035290 A JP 40035290A JP H04209559 A JPH04209559 A JP H04209559A
Authority
JP
Japan
Prior art keywords
package
leads
main surface
package body
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2400352A
Other languages
Japanese (ja)
Inventor
Hironari Ogawa
宏成 小川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2400352A priority Critical patent/JPH04209559A/en
Publication of JPH04209559A publication Critical patent/JPH04209559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce in size and to easily clean flux after soldering by providing a gap between the main surface of a bottom and a mounting board by outer leads of a package body and a protrusion provided at opposite side thereto. CONSTITUTION:Outer leads 8 extended from one side of a package body 6 are bent in a direction of one main surface 6a of the body 6, bent at the ends further outward, and formed flatly. The flatly formed parts are formed at lower side from the surface 6a of the body 6, and a protrusion 9 is provided on the other end surface 6a of the body 6 opposed to the extended ends of the leads 8. The protrusion 9 has substantially the same height as the ends of the leads 8, and a gap is formed between a board 10 and the surface 6a. Thus, even if a pitch of the leads 8 is shortened, the leads can be soldered, reduced in size, and flux after soldering can be easily cleaned.

Description

【発明の詳細な説明】[Detailed description of the invention]

［０００１１ [00011

【産業上の利用分野］この発明は半導体装置のパッケー
ジ形状に関するものである。 ［０００２］ 【従来の技術】従来の半導体装置のパッケージ本体の一
側端面からリードが導出したパッケージとしてシングル
イジライン型のパッケージ（以下、ＳＩＬパッケージと
記す。）がある。図３は前記ＳＩＬパッケージの斜視図
、図４は前記ＳＩＬパッケージの透視平面図を示す。 図において、１はアイランド２上に接合され、その縁部
に多数の電極３を有する半導体素子、４は半導体素子１
の周辺に設けられ、例えば金線などのワイヤ５を介して
、電極３に接続されるリードで、６は内部にリード４の
一部、ワイヤ５．アイランド２及び半導体素子１を樹脂
封止するパッケージ本体、７はリード４のパッケージ本
体６より引き出された部分である。この様なパッケージ
に用いられる半導体素子１の電極３は、リード４の引き
回しの関係で一般には図４に示すように半導体素子１の
３辺に配置されている。 ［０００３］[Industrial Application Field] This invention relates to the package shape of a semiconductor device. 2. Description of the Related Art There is a single-in-line package (hereinafter referred to as an SIL package) as a conventional semiconductor device package in which leads are led out from one side end face of the package body. FIG. 3 shows a perspective view of the SIL package, and FIG. 4 shows a perspective plan view of the SIL package. In the figure, 1 is a semiconductor element bonded onto an island 2 and has a large number of electrodes 3 on its edge, and 4 is a semiconductor element 1.
A lead 6 is provided around the electrode 3 and is connected to the electrode 3 via a wire 5 such as a gold wire. The package body 7 seals the island 2 and the semiconductor element 1 with resin, and is a portion of the lead 4 drawn out from the package body 6. The electrodes 3 of the semiconductor element 1 used in such a package are generally arranged on three sides of the semiconductor element 1 as shown in FIG. 4 due to the routing of the leads 4. [0003]

【発明が解決しようとする課題】図３に示すＳＩＬパッ
ケージはリードを実装基板に挿入するタイプのパッケー
ジである為、外部リードピッチを狭＜　（１，２７ｍｍ
以下）すると実装基板のスルホールの加工が出来ない。 すなわち、パッケージサイズを小型化出来ないという問
題があった。 ［０００４］この発明は上記の問題を解決する為になさ
れたもので、本発明は、パッケージ本体の側端面から導
出されるリードのピッチをより短かくすることができる
半導体装置を得ることを目的としている。 ［０００５］[Problems to be Solved by the Invention] Since the SIL package shown in FIG. 3 is a type of package in which the leads are inserted into the mounting board, the external lead pitch is narrow (1.27 mm
(below), it is not possible to process through-holes on the mounting board. That is, there was a problem in that the package size could not be reduced. [0004] The present invention was made to solve the above problem, and an object of the present invention is to obtain a semiconductor device in which the pitch of the leads led out from the side end surface of the package body can be made shorter. It is said that [0005]

【課題を解決するための手段】この発明に係る半導体装
置は、その先端部主面がパッケージ本体の一側端部から
導出され前記パッケージ本体の一主面側に向けて、この
一主面を越えるとともに、この主面に並行な複数の外部
導出導体と、前記パッケージ本体の一生面に設けられた
凸部とを設けたものである。 ［０００６］[Means for Solving the Problems] In the semiconductor device according to the present invention, the main surface of the tip portion is led out from one end of the package body, and the one main surface is directed toward the one main surface side of the package body. In addition, a plurality of external lead-out conductors are provided in parallel to the main surface, and a convex portion is provided on the entire surface of the package body. [0006]

【作用】この発明における外部導出導体により、そのピ
ッチを小さくすることができ、かつ、外部導出導体と凸
部とによりパッケージの一生面と実装基板との開に間隙
を形成することができる。 ［０００７］[Function] With the external lead-out conductor of the present invention, the pitch thereof can be reduced, and a gap can be formed between the whole surface of the package and the mounting board by the external lead-out conductor and the convex portion. [0007]

【実施例】実施例１４ この発明による一実施例を図１９図２に示し、図１は斜
視図、図２は側面図を示す。図において、６はパッケー
ジ本体、８はパンケージ本体６の一側端面から導出され
た外部リードであって、パッケージ本体６の一生面６ａ
の方向に折り曲げられ、かつ、その先端部はさらに外方
向に折り曲げられると共に平坦に加工されている。この
平坦に加工された部分は、前記パッケージ本体６の一生
面６ａより下側に位置するように形成される。又、外部
リード８が導出されたパッケージ本体６の一側端面と対
向する他の側端部近傍の一生面６ａに凸部９が設けられ
る。この凸部９は、その先端部が前記外部リード先端の
平坦部とほぼ同じ高さになるように形成される。 ［０００８］このような構成によれば複数の外部リード
８の相互のピッチを短かくしてもハンダ付により実装基
板１０に設けられた図示しない配線と接続することがで
きる。また、外部リード８と凸部９とによりパッケージ
６の一生面６ａと実装基板１０間に間隙を形成すること
ができ、ハンダ付後のフラックスの洗浄が容易にできる
。 ［０００９］Embodiment 14 An embodiment according to the present invention is shown in FIGS. 19 and 2, in which FIG. 1 shows a perspective view and FIG. 2 shows a side view. In the figure, 6 is a package body, and 8 is an external lead led out from one side end surface of the pan cage body 6, which is a living surface 6a of the package body 6.
The tip is further bent outward and processed flat. This flattened portion is formed to be located below the lifetime surface 6a of the package body 6. Further, a convex portion 9 is provided on the lifetime surface 6a near the other side end opposite to one side end face of the package body 6 from which the external lead 8 is led out. This convex portion 9 is formed so that its tip portion is approximately at the same height as the flat portion of the tip of the external lead. [0008] According to such a configuration, even if the pitch between the plurality of external leads 8 is shortened, the external leads 8 can be connected to wiring (not shown) provided on the mounting board 10 by soldering. In addition, a gap can be formed between the permanent surface 6a of the package 6 and the mounting board 10 by the external leads 8 and the convex portions 9, and the flux after soldering can be easily cleaned. [0009]

【発明の効果】以上のように、この発明によれば、その
先端部主面がパッケージ本体の一側端部から導出され、
前記パッケージ本体の一主面側に向けて、この一主面を
越えるとともに、この一主面に並行な複数の外部導出導
体と前記パッケージ本体の一生面に設けられた凸部を設
けたもので、パッケージの小型化ができるとともに、ハ
ンダ付後のフラックスの洗浄が容易にできる効果がある
。[Effects of the Invention] As described above, according to the present invention, the main surface of the tip portion is led out from one end of the package body,
A plurality of external lead-out conductors extending beyond the one main surface and parallel to the one main surface toward one main surface of the package main body, and a convex portion provided on the entire surface of the package main body. , the package can be made smaller, and the flux after soldering can be easily cleaned.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】この発明の実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment of the invention.

【図２】この発明の実施例を示す側面図である。FIG. 2 is a side view showing an embodiment of the invention.

【図３】従来の半導体装置を示す斜視図である。FIG. 3 is a perspective view showing a conventional semiconductor device.

【図４】従来の半導体装置のパッケージ本体の平面透視
図である。FIG. 4 is a plan perspective view of a package body of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

６　パッケージ本体 ８　外部リード ９　凸部 6 Package body 8 External lead 9 Convex part

【図１】[Figure 1]

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体装置のパッケージ本体と、その先端
部主面が前記パッケージ本体の一側端部から導出され、
前記パッケージ本体の一主面側に向けて、この一主面を
越えるとともに、この一主面に並行な複数の外部導出導
体と、前記パッケージ本体の前記一主面に設けられた凸
部とを備えた半導体装置。1. A package body of a semiconductor device, and a main surface of a leading end thereof extending from one side end of the package body,
A plurality of external lead-out conductors extending beyond the one main surface and parallel to the one main surface toward the one main surface of the package main body, and a convex portion provided on the one main surface of the package main body. Semiconductor device equipped with
JP2400352A 1990-12-04 1990-12-04 Semiconductor device Pending JPH04209559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2400352A JPH04209559A (en) 1990-12-04 1990-12-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2400352A JPH04209559A (en) 1990-12-04 1990-12-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH04209559A true JPH04209559A (en) 1992-07-30

Family

ID=18510271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2400352A Pending JPH04209559A (en) 1990-12-04 1990-12-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH04209559A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020198342A (en) * 2019-05-31 2020-12-10 三菱電機株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020198342A (en) * 2019-05-31 2020-12-10 三菱電機株式会社 Semiconductor device

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