JPH03230556A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPH03230556A
JPH03230556A JP2026513A JP2651390A JPH03230556A JP H03230556 A JPH03230556 A JP H03230556A JP 2026513 A JP2026513 A JP 2026513A JP 2651390 A JP2651390 A JP 2651390A JP H03230556 A JPH03230556 A JP H03230556A
Authority
JP
Japan
Prior art keywords
tip
lead frame
lead
semiconductor device
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2026513A
Other languages
Japanese (ja)
Inventor
Ichiro Okumura
一郎 奥村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2026513A priority Critical patent/JPH03230556A/en
Publication of JPH03230556A publication Critical patent/JPH03230556A/en
Pending legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/002Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating specially adapted for particular articles or work
    • B23K20/004Wire welding

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent punching of corners, failure in adhesion, and deformation or sagging of a wire by mechanically flattening a tip of an inner lead of a lead frame to increase its area. CONSTITUTION:An area of the tip is increased by mechanically processing a tip of an inner lead 1 of a lead frame for a semiconductor device to have it flattened 1a. By thus increasing the area of the tip by means of flattening the tip of the inner lead 1 with respect to the lead frame etching-molded, a width of the inner lead to be required for wire bonding can be secured, and good wire bonding is possible since a long wire is not necessary.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、集積回路などの多数の電極を有する半導体素
子に金線や銅線などのワイヤを接続するときに使用する
半導体装置用リードフレームに関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a lead frame for a semiconductor device used when connecting wires such as gold wires or copper wires to a semiconductor element having a large number of electrodes such as an integrated circuit.

従来の技術 従来、半導体装置の電極部から外部へリード線を配設す
る場合、エツチング成形されたリードフレームの中央部
に設けられたインナーリードの先端部と半導体装置の上
面に設けられた電極部とを金線または銅線などのワイヤ
でいわゆるワイヤボンディングを行うのが一般的である
Conventional technology Conventionally, when connecting lead wires from the electrode section of a semiconductor device to the outside, the tips of the inner leads provided at the center of an etched lead frame and the electrode section provided on the top surface of the semiconductor device are used. It is common to perform so-called wire bonding with wires such as gold wires or copper wires.

発明が解決しようとする課題 しかしながら、上記従来の半導体装置用リードフレーム
では、半導体装置の多ビン化の進行とともにリードフレ
ームのインナーリード間の先端部間隔が縮小された場合
、エツチングによって除去されるリードフレームの先端
部の間隔の幅がリードフレーム材の板厚により制限され
ることから、ワイヤボンディングに必要なインナーリー
ドの先端幅を十分に確保することが困難となり、ワイヤ
ボンディング時に角打ち、ワイヤたれ、不着などが課題
として発生する。またインナーリードの十分な先端幅を
得るためには、その先端部を半導体チップ上の電極パッ
ドから遠ざけるという方法もとられているが、この場合
、ワイヤの長さが極端に長くなり、ワイヤボンディング
時にワイヤたれやワイヤ変形を引き起こすという課題が
あった。
Problems to be Solved by the Invention However, in the conventional lead frame for semiconductor devices, when the distance between the tips of the inner leads of the lead frame is reduced as the number of bins in semiconductor devices progresses, the lead frame is removed by etching. Since the width of the gap between the tips of the frame is limited by the thickness of the lead frame material, it is difficult to secure a sufficient width of the tips of the inner leads required for wire bonding, resulting in cornering and wire sagging during wire bonding. , non-delivery, etc. occur as issues. In addition, in order to obtain a sufficient tip width of the inner lead, a method is used to move the tip part away from the electrode pad on the semiconductor chip, but in this case, the length of the wire becomes extremely long, making wire bonding difficult. There was a problem that sometimes wire sag or wire deformation occurred.

本発明は、上記従来の課題を解決するものであり、イン
ナーリードの先端部幅を広く確保し、がつワイヤの長さ
を長くすることなく良好なワイヤボンディングを可能と
することのできる半導体装置用リードフレームを提供す
ることを目的とするものである。
The present invention solves the above-mentioned conventional problems, and provides a semiconductor device that can ensure a wide tip width of the inner lead and enable good wire bonding without increasing the length of the wire. The purpose of this invention is to provide lead frames for

課題を解決するための手段 本発明は上記目的を達成するために、半導体装置用リー
ドフレームのインナーリードの先端部を機械加工するこ
とにより扁平にしてその先端部の面積を拡大させたちの
である。
Means for Solving the Problems In order to achieve the above object, the present invention machine-processes the tips of inner leads of lead frames for semiconductor devices to make them flat and increase the area of the tips.

作用 したがって本発明によれば、ワイヤボンディングに必要
なインナーリードの先端部の幅を確保し、かつワイヤの
長さを長くする必要がないため、良好なワイヤボンディ
ングを可能とすることができる。
Therefore, according to the present invention, the width of the tip of the inner lead required for wire bonding is ensured, and there is no need to increase the length of the wire, so that good wire bonding can be performed.

実施例 以下、本発明の一実施例について、第1図〜第3図を参
照しながら説明する。第1図において、1はインナーリ
ード、1aは機械加工により扁平されて中央部より面積
が拡大されたインナーリード先端部、2はダイパッド、
3はアウターリード、4はリードフレーム外枠部である
。第2図は、エツチング成形後のリードフレームのイン
ナーリード1の先端部を示しており、その先端部を機械
加工により扁平にすると第3図に示すような先端部1a
となる。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3. In FIG. 1, 1 is an inner lead, 1a is a tip of the inner lead which has been flattened by machining and has an area enlarged from the center, 2 is a die pad,
3 is an outer lead, and 4 is an outer frame portion of the lead frame. FIG. 2 shows the tip of the inner lead 1 of the lead frame after etching forming, and when the tip is flattened by machining, the tip 1a as shown in FIG.
becomes.

第2図および第3図から明らかなように、エツチング成
形された後のリードフレームのインナーノード1の先端
部を、機械加工する(プレス加工など)ことによって、
その先端部の面積を拡大したものである。
As is clear from FIGS. 2 and 3, by machining (pressing, etc.) the tip of the inner node 1 of the lead frame after etching,
The area of the tip is enlarged.

このようにエツチング成形されたリードフレームに対し
インナーリード1の先端部を扁平にし先端部の面積を広
げることにより、ワイヤボンディングを行う際に必要と
するインナーリードの幅を確保することができ、ワイヤ
の長さも長くする必要がないため良好なワイヤボンディ
ングを行うことができる。
By flattening the tips of the inner leads 1 and increasing the area of the tips for the etched lead frame, it is possible to secure the width of the inner leads required for wire bonding. Since there is no need to increase the length of the wire, good wire bonding can be performed.

発明の効果 本発明は上記実施例より明らかなように、エツチング成
形されたリードフレームのインナーリード先端部を機械
的に扁平にしその面積を広くしたものであり、ワイヤボ
ンディング時の角打ち、不着、ワイヤ変形、たれなどを
防止できるという効果を有するものである。
Effects of the Invention As is clear from the above embodiments, the present invention mechanically flattens the tip of the inner lead of the etched lead frame to increase its area. This has the effect of preventing wire deformation, sag, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例における半導体装置用リード
フレームの部分平面図、第2図は工・ソチング成形後の
リードフレームのインナーリード先端部の拡大斜視図、
第3図は機械加工後のインナーリード先端部の拡大斜視
図である。 1・・・・・・インナーリード、1a・・・・・・機械
加工後のインナーリード先端部。
FIG. 1 is a partial plan view of a lead frame for a semiconductor device according to an embodiment of the present invention, and FIG. 2 is an enlarged perspective view of the tip of the inner lead of the lead frame after machining and sowing molding.
FIG. 3 is an enlarged perspective view of the tip of the inner lead after machining. 1... Inner lead, 1a... Inner lead tip after machining.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の電極部と電気的に接続するインナーリード
を備えた半導体装置用リードフレームにおいて、前記イ
ンナーリードの先端部を扁平にすることによりその面積
を中央部の面積より拡大させた半導体装置用リードフレ
ーム。
A lead frame for a semiconductor device including an inner lead electrically connected to an electrode part of the semiconductor device, wherein the tip of the inner lead is flattened so that its area is larger than that of the center part. flame.
JP2026513A 1990-02-06 1990-02-06 Lead frame for semiconductor device Pending JPH03230556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2026513A JPH03230556A (en) 1990-02-06 1990-02-06 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2026513A JPH03230556A (en) 1990-02-06 1990-02-06 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPH03230556A true JPH03230556A (en) 1991-10-14

Family

ID=12195558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2026513A Pending JPH03230556A (en) 1990-02-06 1990-02-06 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPH03230556A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129493A (en) * 1991-11-05 1993-05-25 Hitachi Cable Ltd Manufacture of lead frame
JPH0878604A (en) * 1994-08-31 1996-03-22 Nec Corp Lead frame for semiconductor device
JPH1012658A (en) * 1996-06-13 1998-01-16 Samsung Electron Co Ltd Semiconductor integrated circuit device having many input / output terminals
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758065A (en) * 1980-09-24 1982-04-07 Iseki Agricult Mach Grain particle dryer
JPS62144349A (en) * 1985-12-19 1987-06-27 Fujitsu Ltd Lead frame for semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5758065A (en) * 1980-09-24 1982-04-07 Iseki Agricult Mach Grain particle dryer
JPS62144349A (en) * 1985-12-19 1987-06-27 Fujitsu Ltd Lead frame for semiconductor device and manufacture thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129493A (en) * 1991-11-05 1993-05-25 Hitachi Cable Ltd Manufacture of lead frame
JPH0878604A (en) * 1994-08-31 1996-03-22 Nec Corp Lead frame for semiconductor device
JPH1012658A (en) * 1996-06-13 1998-01-16 Samsung Electron Co Ltd Semiconductor integrated circuit device having many input / output terminals
US7174626B2 (en) * 1999-06-30 2007-02-13 Intersil Americas, Inc. Method of manufacturing a plated electronic termination

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