JPH0420979A - Control method for copying device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of controlling a copying apparatus controlled by a microcomputer, and particularly to sequence control of a copying process.

[Conventional technology]

Sequence control of the copying process in a microcomputer-controlled copying device determines the timing to energize each load of the copying device based on the count value of timing pulses generated in synchronization with the rotation of a photoreceptor (drum).
For example, one that sequentially drives and executes multiple loads thereby.
If the copying linear speed is 470 m/sec, a timing pulse of 1 sec will provide a resolution of 0.47-. To reduce this control error, it is necessary to shorten the clock cycle.

In order to count timing pulses in such sequence control, a timing pulse is input to the interrupt terminal of a microcomputer, a programmed interrupt processing routine is called for each input, and the timing pulse is counted within the interrupt routine. The solenoid performs a count and compares it with preset timing data, and if a match is found, the solenoid responds to that timing.

A method has been adopted for controlling the on/off of loads necessary for the copying process, such as clutches, erasers, various bias power supplies, etc. (for example, Japanese Patent Publication No. 39232/1983).

Before and after the execution of this interrupt routine, it is necessary to execute program processing each time to save and restore the data of the microcomputer's accumulator, registers, and flags to a specific memory, and it takes a considerable amount of processing time (several tens of minutes). (μsec to several hundred μ5 ec), which increases the time it takes to execute one interrupt processing program and has the problem of affecting other controls as well.

There is also a method of sharing functions among multiple microcomputers, but this requires information transmission between multiple microcomputers, which complicates control and increases costs.

In recent years, as copying devices have become more versatile, multifunctional, and complex, the number of programs that are controlled has also increased. Furthermore, as programming languages have come to be used, the program execution time has increased, and the above-mentioned problems have been further exacerbated.

As a countermeasure for this, an independent hard counter in the microcomputer counts timing pulses, generates an interrupt routine every time the counter overflows, counts the number of interrupts in the interrupt routine, and uses this count value as timing data. It is known that the load is controlled when a comparison is made and a match is found.

[Problem to be solved by the invention]

However, although counting is performed using a hard counter, the number of overflows is counted by a microcomputer and the microcomputer compares this counted value with timing data.

If the yf-A flow period is short, the load on the program operation of the microcomputer becomes large. On the other hand, if the overflow period is long, there are drawbacks such as increased timing errors.

The present invention is highly adaptable to photoconductor synchronization pulses with high resolution (photoconductor movement amount/small 1 pulse = short period), and is suitable for increasing the speed, multifunction, and precision of copying machines. The purpose of this invention is to provide a method for controlling a copy sequence.

[Means to solve the problem]

In order to achieve the above object, one aspect of the present invention is to control a copying process based on a count value of photoreceptor synchronization pulses.

Timing storage means for serially storing timing data indicating timing at which a load should be switched on/off for a plurality of timings, and serially storing on/off data of the load at each of the timings for a plurality of timings. A plurality of timing data and load on/off data corresponding to each of the timing data are serially written in each of the on/off data storage means in timing order.

On/off of the load is determined based on the earliest on/off data of the on/off data storage means.

The synchronization pulses generated one pulse per predetermined amount of movement of the photoreceptor are counted, the count data is compared with the earliest timing data serially stored in the timing storage means, and if they match, a match signal is generated, and the match signal is The timing storage means serially advances the data one step to update the earliest timing data to the next one, and the on/off data storage means serially advances the data one step to update the earliest on/off data. Update to:

[Operation] According to this, a plurality of load on/off timing data and on/off data are serially stored in the timing storage means and the on/off data storage means, and the earliest data of the on/off data storage means is stored in the timing storage means and the on/off data storage means. Turn on/off the load based on Also.

When the count value of the mineral synchronization pulse and the earliest timing data match, a coincidence signal is generated, and the coincidence signal causes the timing storage means to serially advance the data by one step, and transfer the earliest timing data to the next one. In addition, the on/off data storage means also serially advances the data by one step to update the earliest on/off data to the next one.

Therefore, since there is no need to execute interrupt processing using the synchronization pulse, it is possible to use the synchronization pulse with high resolution (the amount of photoreceptor movement/1 pulse is small) and realize highly accurate sequence timing control. In addition, if the leapfrog that controls on/off of various loads in the sequence control of the copying process is used for other controls, programs can be executed at high density, increasing the operating efficiency of the microcomputer. Since the actual burden and errors on the microcomputer are reduced, a copying apparatus suitable for high speed, multifunctionality, and high precision is provided.

Further, since the load is turned on/off directly on the hardware by the coincidence signal, no time delay occurs in controlling the copying process sequence.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

〔Example〕

FIG. 3 shows the main parts of a copying machine to which an embodiment of the present invention is applied.

This copying machine is of a fixed original type, and an optical system 3 including an exposure lamp 3a and a large number of mirrors optically scans an original 2 placed on a contact glass l in synchronization with the rotation of a photoreceptor 4.

At this time, the light that scanned the original (light reflected from the original) is irradiated onto the photosensitive surface of the photoreceptor 4, but the photosensitive surface of the photoreceptor 4 is uniformly charged by the charger 5 before being irradiated with this light. The charge outside the image forming area is removed by the eraser 6. Therefore, when this image forming area is irradiated with reflected light from the original, photoconduction occurs depending on the strength of the light,
An electrostatic latent image is formed.

This electrostatic latent image is developed! 7, toner is applied.

The attached toner, ie, the developed image, is transferred to the recording paper by the transfer charger 8. Thereafter, residual toner is removed from the photosensitive surface of the photoconductor 4 by a cleaner 9, and the recording paper is fixed by a fixing device 10.

Further, an encoder LL is coupled to the rotation axis of the photoconductor 4, and this encoder 11 generates pulses synchronized with the rotation of the photoconductor 4 and controls each of sequence control circuits 40, 50, and 60, which will be described later. to the counter circuit.

FIG. 1 shows an electric control section that controls each of these constituent elements, and FIG. 2 shows the configuration of the sequence control circuit 40 shown in FIG. 1.

The electric control section shown in FIG. 1 includes a microcomputer (hereinafter referred to as CP, U) 21. which controls the entire sequence of the copying process. CPU 22 for controlling the operating section. CPU21
The RO is connected to the address bus, control path, data bus, etc., and stores fixed data and control programs.
M23. RA that reads and writes copy data and various flags, etc.
M24, obtains signals from mechanical condition sensors 25;

An I10 controller circuit (hereinafter referred to as PIO) 28 outputs signals to control some loads 27 such as the drive system, development system, paper feeding/discharging system, etc. via the driver 26, and determines the timing of each process in the copying sequence. sequence control circuits 40, 50, and 60. Sequence control circuit 40.50. and 60. Decoder 29. a latch circuit 30 comprising as many latches as the number of loads required for sequence control of a series of copying processes;
When an abnormal voltage occurs, a reset signal is sent to the CPU21.22. P
IO28, sequence control circuit 40.50.6
It is composed of a power supply voltage monitoring circuit 31 that outputs to 0, and the like.

The CPU 21 receives the key human power signal from the CPU 22 and the PI
Go to the O28 human power signal and judge the copying process conditions and CP
A series of loads that are output as display data to U22 or that are directly involved in the sequence of the copying process depending on the copy mode (two loads other than load 27 shown in Figure 2)
Load on/off data and load on/off timing data for on/off control of loads other than the above are simply referred to as loads.

As shown in FIG. 2, the sequence control circuit 40 includes a counter circuit 41. Multiple comparison registers 421-42
n, control word register 43, comparison circuit 44.
Data path buffer 45° Multiple latch data registers 461-46n and multiple latch circuits 471-4
7n, etc.

Sequence control of the copying process is performed by manually selecting the desired number of copies 9 and selecting the magnification 9 using keys from the operation unit (not shown).
After the duplex mode, peripherals, etc. have been selected, the copy start key is pressed to start. The address signal of the CPU 21 is decoded by the decoder 29, and one of the sequence control circuits 40, 50, and 60 is selected. In this embodiment, one of the sequence control circuits corresponds to sequence control for one sheet of paper, and in order to perform sequence control for each of the plurality of sheets of paper in the paper conveyance path in the copying machine, In this example, the maximum number is 3, so Silkens Control @MI! 40.5 o.

3 circuits consisting of 60 40 → 50 → 60 → 40 → 5
They are used in order from 0 to 60.

Control word register 43 in sequence control circuit 40. Comparison registers 421 to 42n, counter circuit 41. Latch data registers 461 to 46n are selected by address signals AO and AI from CP'U21, and control signals are sent to control word register 43 by write signal WR from CPU21 to two comparison registers 42. ~42n has timing data,
Load on/off data is written to latch data registers 461 to 46n, respectively. Note that before starting the counter circuit 41, the comparison register 421 is
42n are written with respective timing data in the order of the loads to be controlled, and launch data registers 461 to 46n are written with on/off data of the respective loads in the order of the loads to be controlled by the CPU 21.

Here, when the copying sequence is started by the CPU 21 and a main motor ON signal is output from the PIO 28, the encoder 11 coupled to the rotation shaft of the photoreceptor 4 rotates, and a timing pulse synchronized with the rotation of the photoreceptor is sent to the sequence control circuit. 40, 50, and 60 respectively. To explain only the sequence control circuit 40 here, after a certain period of time has elapsed, C
The PU 21 outputs a count start signal C8, and the counter circuit 41 starts counting operation. When the count value from the two-power counter circuit 41 and the value in the comparison register 421 become the same, the comparison circuit 44 outputs a match signal from the comparison circuit 44, and the match signal causes the latch data register 421 to
61 on/off data is latched by the launch circuits 471 to 47n, and the load is turned on/off in response to the latch output.
It will be turned off.

At the same time, the match signal output from the comparison circuit 44 is transmitted to the comparison registers 421 to 42n and the latch data register 4.
It is input to the WR terminals 61 to 46n and turns on/off the next load.
The on/off data of the load (data in the latch data register 462) for turning off the load is stored in the latch data register 46.
Written to 1.

Timing data (data in comparison register 422) for turning on/off the next load is written to comparison register 421. At this time, the data in the latch data register 463 is transferred to the latch data register 462, and the data in the latch data register 464 is transferred to the latch data register 463.
Then, data in each latch data register is shifted such that the data in the launch data register 46n is transferred to the latch data register 46n-1. Similarly, the data in the comparison register 423 is transferred to the comparison register 422, the data in the comparison register 424 is transferred to the comparison register 423, ..., the data in the comparison register 42n is transferred to the comparison register 42n-1, and so on. A shift takes place.

When the photoreceptor 4 further rotates and the counter circuit 41 performs the same count as the data in the comparison register 421, the comparison circuit 44 outputs a coincidence signal in the same manner as described above. The latch circuits 471 to 47n send the signal to the launch data register 461.
The clock input is doubled to latch the data of
The load is turned on/off in response to the latch output. At the same time, the data of the comparison register and the on/off data of the load are shifted as described above.

This operation is repeated, and when the copying operation for one sheet is completed and the paper is ejected to the paper ejection tray, the CPU 21 stops the counting operation of the sequence control circuit 40 and resets (clears) the counter to 0. In the case of copying one sheet, the copying operation ends with this, but in the case of multiple copies, in order to execute the first copying operation, the timing for each load of the next copy is stored in the comparison registers 421 to 42n. data to latch data registers 461-4
Load on/off data for turning on/off each load of the next copy is set in 6n.

FIG. 4 shows the operation timing of a series of loads related to the sequence of the copying process.

First, the comparison port of the sequence control circuit 40 @44
When a match signal is output from
The load on/off data written in 1 is latched by latch circuits 471 to 47n. This latch output allows cleaning bias and pre-cleaning charger.

Pre-transfer static elimination, static elimination lamp, development bias, and eraser are turned on. In addition, cleaning bias, pre-cleaning charger, and pre-transfer static elimination.

The static elimination lamp, qi image bias, and eraser ON signals are set at the 4th Il! These are the first timing data and load on/off data shown in dotted line A in the timing chart of R. These data are stored in advance by the CPU 21 in the comparison register 421 and latch data register 46.
It is written in 1.

Further, the match signal is input to the WR terminals of the latch data registers 461 to 46n via the AND gate, and the next load written in the latch data register 462 is turned on/off.
The on/off data of the load to be turned off (on data of the paper feed clutch) is written to the latch pig register 461, the data written to the latch data register 463 is written to the latch data register 462,..., the latch data register 46
The data written in n is stored in the latch data register 46.
n-1, respectively. Similarly, the match signal is input to the WR terminals of the comparison circuits 421 to 42n via the AND gate, and the next ON/OFF signal written in the comparison circuit 422 is
The timing data for turning off (dotted line B in FIG. 4) is written in the comparison register 421, the data written in the comparison register 428 is written in the comparison circuit 422, etc., the comparison circuit 4
The data written in 2n is sent to comparison circuit 42n-1.

Each is written. i.e. by a match signal.

The data will be shifted and the data in latch data register 461 and comparison register 42H will be updated.

When the photoreceptor 4 rotates further and the count value becomes equal to the next timing data (paper feed clutch on data), the latch data register 46 is activated by a match signal from the comparison circuit 44.
The load on/off data (paper feed clutch on data) written in 1 is latched by the latch circuits 471 to 47n, and the load is turned on/off in response to the latch output.

Note that, similarly to the above, the load on/off data (halogen lamp on data) for turning on/off the next load written in the latch data register 462 by the coincidence signal
is written to the latch data register 461, and the next timing data (fourth timing data) written to the comparison register 422
Dotted line C) in the figure is written to the comparison register 421,
Data is updated.

Furthermore, when the photoreceptor 4 rotates and the count value becomes equal to the next timing data (halogen lamp on data), the load on/off data written in the latch data register 461 ( The halogen lamp ON data) is latched by the latch circuits 471 to 47n, and the load is turned on/off in accordance with the latch output.

Note that, in the same manner as described above, the load on/off data (calling solenoid on data) that turns on/off the next load written in the latch data register 462 is written in the latch data register 461 and compared. The next timing data written in the register 422 (dotted line D in FIG. 4) is written in the comparison register 421, and the data is updated.

Furthermore, when the photoreceptor 4 rotates and the count value becomes equal to the next timing data (calling solenoid ON data), the load on/off data written in the latch data register 461 (
Call solenoid on data) is latch circuit 471~
47n, and the load is turned on/off in response to the latch output. Similarly to the above, the load on/off data (charger on data) for turning on/off the next load written in the latch data register 462 is written in the latch data register 461 and compared. The next timing data (dotted line E in FIG. 4) written in the register 422 is transferred to the comparison register 421.
is written and the data is updated.

Furthermore, when the photoreceptor 4 rotates and the count value becomes equal to the next timing data (charger on data), the load on/off data written in the latch data register 461 ( Charger-on data) is launched to latch circuits 471 to 47n.

The load is turned on/off in response to the latch output.

Similarly to the above, the load on/off data (scanner motor start on data) for turning on/off the next load written in the latch data register 462 is written in the latch data register 461 by the coincidence signal. , the next timing data written to the comparison register 422 (dotted line F in FIG. 4) is written to the comparison register 42. is written and the data is updated.

Similarly, the load on/off data is latched using the match signal from the comparison circuit 44, and the load on/off control is executed using the latch output. This match signal also updates the data (
data shift) is performed. In other words, n comparison registers and latch data registers are sufficient to correspond to the timing and on/off data for controlling the load necessary for one copy operation.

When the copying operation for one sheet is completed, the CPU 21 registers the comparison registers 421 to 42n and the latch data registers 461 to 42n.
46n. If the number of copies is one, the copying operation ends, but if there are a plurality of copies, the next copy sequence is started.

It should be noted that sequence controls ryJM40.50° and 60 must be provided for the number of sheets of paper that are simultaneously present on the conveyance path in the copying machine. , corresponding sequence control circuits 40.50. and 3 of 60
It is equipped with two things. As a result, the sequence control circuit for each paper is 40 → 50 → 60 → 40 → 50 →
Use in order from 60 to...

As described above, the timing pulse signal of the photoreceptor 4 is
A hard counter circuit 41 independent from U21 performs counting, and when the count value matches the timing data written in the comparison register in advance, a match signal is issued, and this signal causes the load written in the latch data register 46 to be counted. The on/off data of the latch circuits 471 to 47n
The latch is latched by means, and the load is controlled in accordance with the latch output. Note that during load sequence control.

Timing data and load on/off data are updated independently of the CPU 21.

[Effects of CRWJJ] As described above, according to the present invention, there is no need to execute interrupt processing using synchronization pulses. Realizes precise sequence timing control.

In addition, while on/off control of various loads is being performed in the sequence control of the copying process, if the microcomputer is used for other controls, programs can be executed at high density, increasing the operating efficiency of the microcomputer. Since the actual burden and errors on the microcomputer are reduced, a copying apparatus suitable for high speed, multifunctionality, and high precision is provided.

Further, since the load is turned on/off directly on the hardware by the coincidence signal, no time delay occurs in controlling the copying process sequence.

[Brief explanation of drawings]

FIG. 1 shows a block diagram of an electrical control section of a copying machine according to an embodiment of the present invention. FIG. 2 shows the sequence control circuit 4 shown in FIG.
FIG. 2 is a block diagram showing the configuration of 0. FIG. 3 shows a block diagram of a copying machine controlled by the electric control section shown in FIG. FIG. 4 shows an operational timing chart of loads involved in the copying process sequence shown in FIG. 1: Contact glass 2: Original 3: Optical system 3a = Exposure lamp 4 Nissa θ books (6) 5: Charger 6: Eraser 7: Developer 8: Transfer charger 9: Cleaner 10: Fixing amount 11: Encoder 12: Photoreceiver 21: Microcomputer 22: Microcomputer 23: ROM2
4: RAM 25
: Mechanical force status sensors 26 = driver
27: Load 28: I10 controller
29: Decoder 30 = latch circuit
31: Power supply voltage monitoring circuit 40.
43: Control word register 44: Comparison circuit 45: Data path buffer 1161-46n: Latch data register (on/off data storage register 471-47n: Latch circuit voice ■

Claims (1)

[Claims] In controlling a copying process based on a count value of a photoreceptor synchronization pulse, a timing storage means serially stores timing data indicating timing at which a load should be switched on/off for a plurality of timings. and on/off data storage means for serially storing load on/off data at each of the timings for a plurality of timings. Writes off data serially in timing order, determines on/off of the load based on the earliest on/off data of the on/off data storage means, and generates a synchronization pulse that generates one pulse per predetermined amount of movement of the photoreceptor. The count data is compared with the earliest timing data serially stored in the timing storage means, and if they match, a coincidence signal is generated, and the coincidence signal causes the timing storage means to serially advance the data by one step to the earliest timing data. A copying apparatus characterized in that the previous timing data is updated to the next one, and the on/off data storage means also serially advances the data by one step to update the earliest on/off data to the next one. control method.